Lines Matching +full:clk +full:- +full:out +full:- +full:strength
1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2014-2015 Lucas Stach <dev@lynxeye.de>
8 #include <linux/clk.h>
10 #include <linux/dma-mapping.h>
34 #define COMMAND_TRANS_SIZE(size) ((((size) - 1) & 0xf) << 20)
40 #define COMMAND_CLE_SIZE(size) ((((size) - 1) & 0x3) << 4)
41 #define COMMAND_ALE_SIZE(size) ((((size) - 1) & 0xf) << 0)
156 #define OFFSET(val, off) ((val) < (off) ? 0 : (val) - (off))
174 struct clk *clk; member
207 int bytes_per_step = DIV_ROUND_UP(BITS_PER_STEP_RS * chip->ecc.strength, in tegra_nand_ooblayout_rs_ecc()
211 return -ERANGE; in tegra_nand_ooblayout_rs_ecc()
213 oobregion->offset = SKIP_SPARE_BYTES; in tegra_nand_ooblayout_rs_ecc()
214 oobregion->length = round_up(bytes_per_step * chip->ecc.steps, 4); in tegra_nand_ooblayout_rs_ecc()
222 return -ERANGE; in tegra_nand_ooblayout_no_free()
234 int bytes_per_step = DIV_ROUND_UP(BITS_PER_STEP_BCH * chip->ecc.strength, in tegra_nand_ooblayout_bch_ecc()
238 return -ERANGE; in tegra_nand_ooblayout_bch_ecc()
240 oobregion->offset = SKIP_SPARE_BYTES; in tegra_nand_ooblayout_bch_ecc()
241 oobregion->length = round_up(bytes_per_step * chip->ecc.steps, 4); in tegra_nand_ooblayout_bch_ecc()
256 isr = readl_relaxed(ctrl->regs + ISR); in tegra_nand_irq()
257 dma = readl_relaxed(ctrl->regs + DMA_MST_CTRL); in tegra_nand_irq()
258 dev_dbg(ctrl->dev, "isr %08x\n", isr); in tegra_nand_irq()
266 * Correctable OR Un-correctable errors occurred in the DMA transfer... in tegra_nand_irq()
269 ctrl->last_read_error = true; in tegra_nand_irq()
272 complete(&ctrl->command_complete); in tegra_nand_irq()
275 dev_err(ctrl->dev, "FIFO underrun\n"); in tegra_nand_irq()
278 dev_err(ctrl->dev, "FIFO overrun\n"); in tegra_nand_irq()
282 writel_relaxed(dma, ctrl->regs + DMA_MST_CTRL); in tegra_nand_irq()
283 complete(&ctrl->dma_complete); in tegra_nand_irq()
287 writel_relaxed(isr, ctrl->regs + ISR); in tegra_nand_irq()
316 dev_err(ctrl->dev, "Tegra NAND controller register dump\n"); in tegra_nand_dump_reg()
323 reg = readl_relaxed(ctrl->regs + (i * 4)); in tegra_nand_dump_reg()
324 dev_err(ctrl->dev, "%s: 0x%08x\n", reg_name, reg); in tegra_nand_dump_reg()
332 disable_irq(ctrl->irq); in tegra_nand_controller_abort()
335 writel_relaxed(0, ctrl->regs + DMA_MST_CTRL); in tegra_nand_controller_abort()
336 writel_relaxed(0, ctrl->regs + COMMAND); in tegra_nand_controller_abort()
339 isr = readl_relaxed(ctrl->regs + ISR); in tegra_nand_controller_abort()
340 writel_relaxed(isr, ctrl->regs + ISR); in tegra_nand_controller_abort()
341 dma = readl_relaxed(ctrl->regs + DMA_MST_CTRL); in tegra_nand_controller_abort()
342 writel_relaxed(dma, ctrl->regs + DMA_MST_CTRL); in tegra_nand_controller_abort()
344 reinit_completion(&ctrl->command_complete); in tegra_nand_controller_abort()
345 reinit_completion(&ctrl->dma_complete); in tegra_nand_controller_abort()
347 enable_irq(ctrl->irq); in tegra_nand_controller_abort()
355 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller); in tegra_nand_cmd()
361 for (op_id = 0; op_id < subop->ninstrs; op_id++) { in tegra_nand_cmd()
366 instr = &subop->instrs[op_id]; in tegra_nand_cmd()
368 switch (instr->type) { in tegra_nand_cmd()
372 writel_relaxed(instr->ctx.cmd.opcode, in tegra_nand_cmd()
373 ctrl->regs + CMD_REG1); in tegra_nand_cmd()
376 writel_relaxed(instr->ctx.cmd.opcode, in tegra_nand_cmd()
377 ctrl->regs + CMD_REG2); in tegra_nand_cmd()
385 addrs = &instr->ctx.addr.addrs[offset]; in tegra_nand_cmd()
390 naddrs -= i; in tegra_nand_cmd()
394 writel_relaxed(addr1, ctrl->regs + ADDR_REG1); in tegra_nand_cmd()
395 writel_relaxed(addr2, ctrl->regs + ADDR_REG2); in tegra_nand_cmd()
414 memcpy(®, instr->ctx.data.buf.out + offset, size); in tegra_nand_cmd()
416 writel_relaxed(reg, ctrl->regs + RESP); in tegra_nand_cmd()
425 cmd |= COMMAND_GO | COMMAND_CE(ctrl->cur_cs); in tegra_nand_cmd()
426 writel_relaxed(cmd, ctrl->regs + COMMAND); in tegra_nand_cmd()
427 ret = wait_for_completion_timeout(&ctrl->command_complete, in tegra_nand_cmd()
430 dev_err(ctrl->dev, "COMMAND timeout\n"); in tegra_nand_cmd()
433 return -ETIMEDOUT; in tegra_nand_cmd()
437 reg = readl_relaxed(ctrl->regs + RESP); in tegra_nand_cmd()
438 memcpy(instr_data_in->ctx.data.buf.in + offset, ®, size); in tegra_nand_cmd()
464 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller); in tegra_nand_select_target()
466 ctrl->cur_cs = nand->cs[die_nr]; in tegra_nand_select_target()
474 tegra_nand_select_target(chip, op->cs); in tegra_nand_exec_op()
485 if (chip->ecc.algo == NAND_ECC_ALGO_BCH && enable) in tegra_nand_hw_ecc()
486 writel_relaxed(nand->bch_config, ctrl->regs + BCH_CONFIG); in tegra_nand_hw_ecc()
488 writel_relaxed(0, ctrl->regs + BCH_CONFIG); in tegra_nand_hw_ecc()
491 writel_relaxed(nand->config_ecc, ctrl->regs + CONFIG); in tegra_nand_hw_ecc()
493 writel_relaxed(nand->config, ctrl->regs + CONFIG); in tegra_nand_hw_ecc()
500 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller); in tegra_nand_page_xfer()
506 tegra_nand_select_target(chip, chip->cur_cs); in tegra_nand_page_xfer()
509 writel_relaxed(NAND_CMD_READ0, ctrl->regs + CMD_REG1); in tegra_nand_page_xfer()
510 writel_relaxed(NAND_CMD_READSTART, ctrl->regs + CMD_REG2); in tegra_nand_page_xfer()
512 writel_relaxed(NAND_CMD_SEQIN, ctrl->regs + CMD_REG1); in tegra_nand_page_xfer()
513 writel_relaxed(NAND_CMD_PAGEPROG, ctrl->regs + CMD_REG2); in tegra_nand_page_xfer()
517 /* Lower 16-bits are column, by default 0 */ in tegra_nand_page_xfer()
521 addr1 |= mtd->writesize; in tegra_nand_page_xfer()
522 writel_relaxed(addr1, ctrl->regs + ADDR_REG1); in tegra_nand_page_xfer()
524 if (chip->options & NAND_ROW_ADDR_3) { in tegra_nand_page_xfer()
525 writel_relaxed(page >> 16, ctrl->regs + ADDR_REG2); in tegra_nand_page_xfer()
532 dma_addr = dma_map_single(ctrl->dev, buf, mtd->writesize, dir); in tegra_nand_page_xfer()
533 ret = dma_mapping_error(ctrl->dev, dma_addr); in tegra_nand_page_xfer()
535 dev_err(ctrl->dev, "dma mapping error\n"); in tegra_nand_page_xfer()
536 return -EINVAL; in tegra_nand_page_xfer()
539 writel_relaxed(mtd->writesize - 1, ctrl->regs + DMA_CFG_A); in tegra_nand_page_xfer()
540 writel_relaxed(dma_addr, ctrl->regs + DATA_PTR); in tegra_nand_page_xfer()
544 dma_addr_oob = dma_map_single(ctrl->dev, oob_buf, mtd->oobsize, in tegra_nand_page_xfer()
546 ret = dma_mapping_error(ctrl->dev, dma_addr_oob); in tegra_nand_page_xfer()
548 dev_err(ctrl->dev, "dma mapping error\n"); in tegra_nand_page_xfer()
549 ret = -EINVAL; in tegra_nand_page_xfer()
553 writel_relaxed(oob_len - 1, ctrl->regs + DMA_CFG_B); in tegra_nand_page_xfer()
554 writel_relaxed(dma_addr_oob, ctrl->regs + TAG_PTR); in tegra_nand_page_xfer()
571 writel_relaxed(dma_ctrl, ctrl->regs + DMA_MST_CTRL); in tegra_nand_page_xfer()
574 COMMAND_CE(ctrl->cur_cs); in tegra_nand_page_xfer()
586 writel_relaxed(cmd, ctrl->regs + COMMAND); in tegra_nand_page_xfer()
588 ret = wait_for_completion_timeout(&ctrl->command_complete, in tegra_nand_page_xfer()
591 dev_err(ctrl->dev, "COMMAND timeout\n"); in tegra_nand_page_xfer()
594 ret = -ETIMEDOUT; in tegra_nand_page_xfer()
598 ret = wait_for_completion_timeout(&ctrl->dma_complete, in tegra_nand_page_xfer()
601 dev_err(ctrl->dev, "DMA timeout\n"); in tegra_nand_page_xfer()
604 ret = -ETIMEDOUT; in tegra_nand_page_xfer()
611 dma_unmap_single(ctrl->dev, dma_addr_oob, mtd->oobsize, dir); in tegra_nand_page_xfer()
614 dma_unmap_single(ctrl->dev, dma_addr, mtd->writesize, dir); in tegra_nand_page_xfer()
623 void *oob_buf = oob_required ? chip->oob_poi : NULL; in tegra_nand_read_page_raw()
626 mtd->oobsize, page, true); in tegra_nand_read_page_raw()
633 void *oob_buf = oob_required ? chip->oob_poi : NULL; in tegra_nand_write_page_raw()
636 mtd->oobsize, page, false); in tegra_nand_write_page_raw()
643 return tegra_nand_page_xfer(mtd, chip, NULL, chip->oob_poi, in tegra_nand_read_oob()
644 mtd->oobsize, page, true); in tegra_nand_read_oob()
651 return tegra_nand_page_xfer(mtd, chip, NULL, chip->oob_poi, in tegra_nand_write_oob()
652 mtd->oobsize, page, false); in tegra_nand_write_oob()
659 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller); in tegra_nand_read_page_hwecc()
661 void *oob_buf = oob_required ? chip->oob_poi : NULL; in tegra_nand_read_page_hwecc()
672 /* No correctable or un-correctable errors, page must have 0 bitflips */ in tegra_nand_read_page_hwecc()
673 if (!ctrl->last_read_error) in tegra_nand_read_page_hwecc()
677 * Correctable or un-correctable errors occurred. Use DEC_STAT_BUF in tegra_nand_read_page_hwecc()
685 ctrl->last_read_error = false; in tegra_nand_read_page_hwecc()
686 dec_stat = readl_relaxed(ctrl->regs + DEC_STAT_BUF); in tegra_nand_read_page_hwecc()
710 if (fail_sec_flag ^ GENMASK(chip->ecc.steps - 1, 0)) { in tegra_nand_read_page_hwecc()
711 mtd->ecc_stats.failed += hweight8(fail_sec_flag); in tegra_nand_read_page_hwecc()
717 * enough to figure out if a page is really just erased. in tegra_nand_read_page_hwecc()
719 * erased or if error correction just failed for all sub- in tegra_nand_read_page_hwecc()
726 for_each_set_bit(bit, &fail_sec_flag, chip->ecc.steps) { in tegra_nand_read_page_hwecc()
727 u8 *data = buf + (chip->ecc.size * bit); in tegra_nand_read_page_hwecc()
728 u8 *oob = chip->oob_poi + nand->ecc.offset + in tegra_nand_read_page_hwecc()
729 (chip->ecc.bytes * bit); in tegra_nand_read_page_hwecc()
731 ret = nand_check_erased_ecc_chunk(data, chip->ecc.size, in tegra_nand_read_page_hwecc()
732 oob, chip->ecc.bytes, in tegra_nand_read_page_hwecc()
734 chip->ecc.strength); in tegra_nand_read_page_hwecc()
736 mtd->ecc_stats.failed++; in tegra_nand_read_page_hwecc()
738 mtd->ecc_stats.corrected += ret; in tegra_nand_read_page_hwecc()
759 mtd->ecc_stats.corrected += max_corr_cnt * hweight8(corr_sec_flag); in tegra_nand_read_page_hwecc()
769 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller); in tegra_nand_write_page_hwecc()
770 void *oob_buf = oob_required ? chip->oob_poi : NULL; in tegra_nand_write_page_hwecc()
788 unsigned int rate = clk_get_rate(ctrl->clk) / 1000000; in tegra_nand_setup_timing()
792 val = DIV_ROUND_UP(max3(timings->tAR_min, timings->tRR_min, in tegra_nand_setup_timing()
793 timings->tRC_min), period); in tegra_nand_setup_timing()
796 val = DIV_ROUND_UP(max(max(timings->tCS_min, timings->tCH_min), in tegra_nand_setup_timing()
797 max(timings->tALS_min, timings->tALH_min)), in tegra_nand_setup_timing()
801 val = DIV_ROUND_UP(max(timings->tRP_min, timings->tREA_max) + 6000, in tegra_nand_setup_timing()
805 reg |= TIMING_TWB(OFFSET(DIV_ROUND_UP(timings->tWB_max, period), 1)); in tegra_nand_setup_timing()
806 reg |= TIMING_TWHR(OFFSET(DIV_ROUND_UP(timings->tWHR_min, period), 1)); in tegra_nand_setup_timing()
807 reg |= TIMING_TWH(OFFSET(DIV_ROUND_UP(timings->tWH_min, period), 1)); in tegra_nand_setup_timing()
808 reg |= TIMING_TWP(OFFSET(DIV_ROUND_UP(timings->tWP_min, period), 1)); in tegra_nand_setup_timing()
809 reg |= TIMING_TRH(OFFSET(DIV_ROUND_UP(timings->tREH_min, period), 1)); in tegra_nand_setup_timing()
811 writel_relaxed(reg, ctrl->regs + TIMING_1); in tegra_nand_setup_timing()
813 val = DIV_ROUND_UP(timings->tADL_min, period); in tegra_nand_setup_timing()
816 writel_relaxed(reg, ctrl->regs + TIMING_2); in tegra_nand_setup_timing()
822 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller); in tegra_nand_setup_interface()
842 static int tegra_nand_get_strength(struct nand_chip *chip, const int *strength, in tegra_nand_get_strength() argument
849 bool maximize = base->ecc.user_conf.flags & NAND_ECC_MAXIMIZE_STRENGTH; in tegra_nand_get_strength()
854 * maximize the BCH strength. in tegra_nand_get_strength()
860 strength_sel = strength[strength_len - i - 1]; in tegra_nand_get_strength()
862 strength_sel = strength[i]; in tegra_nand_get_strength()
864 if (strength_sel < requirements->strength) in tegra_nand_get_strength()
870 bytes_per_page = round_up(bytes_per_step * chip->ecc.steps, 4); in tegra_nand_get_strength()
872 /* Check whether strength fits OOB */ in tegra_nand_get_strength()
873 if (bytes_per_page < (oobsize - SKIP_SPARE_BYTES)) in tegra_nand_get_strength()
877 return -EINVAL; in tegra_nand_get_strength()
882 const int *strength; in tegra_nand_select_strength() local
885 switch (chip->ecc.algo) { in tegra_nand_select_strength()
888 if (chip->options & NAND_IS_BOOT_MEDIUM) { in tegra_nand_select_strength()
889 strength = rs_strength_bootable; in tegra_nand_select_strength()
892 strength = rs_strength; in tegra_nand_select_strength()
898 if (chip->options & NAND_IS_BOOT_MEDIUM) { in tegra_nand_select_strength()
899 strength = bch_strength_bootable; in tegra_nand_select_strength()
902 strength = bch_strength; in tegra_nand_select_strength()
907 return -EINVAL; in tegra_nand_select_strength()
910 return tegra_nand_get_strength(chip, strength, strength_len, in tegra_nand_select_strength()
916 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller); in tegra_nand_attach_chip()
918 nanddev_get_ecc_requirements(&chip->base); in tegra_nand_attach_chip()
924 if (chip->bbt_options & NAND_BBT_USE_FLASH) in tegra_nand_attach_chip()
925 chip->bbt_options |= NAND_BBT_NO_OOB; in tegra_nand_attach_chip()
927 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; in tegra_nand_attach_chip()
928 chip->ecc.size = 512; in tegra_nand_attach_chip()
929 chip->ecc.steps = mtd->writesize / chip->ecc.size; in tegra_nand_attach_chip()
930 if (requirements->step_size != 512) { in tegra_nand_attach_chip()
931 dev_err(ctrl->dev, "Unsupported step size %d\n", in tegra_nand_attach_chip()
932 requirements->step_size); in tegra_nand_attach_chip()
933 return -EINVAL; in tegra_nand_attach_chip()
936 chip->ecc.read_page = tegra_nand_read_page_hwecc; in tegra_nand_attach_chip()
937 chip->ecc.write_page = tegra_nand_write_page_hwecc; in tegra_nand_attach_chip()
938 chip->ecc.read_page_raw = tegra_nand_read_page_raw; in tegra_nand_attach_chip()
939 chip->ecc.write_page_raw = tegra_nand_write_page_raw; in tegra_nand_attach_chip()
940 chip->ecc.read_oob = tegra_nand_read_oob; in tegra_nand_attach_chip()
941 chip->ecc.write_oob = tegra_nand_write_oob; in tegra_nand_attach_chip()
943 if (chip->options & NAND_BUSWIDTH_16) in tegra_nand_attach_chip()
944 nand->config |= CONFIG_BUS_WIDTH_16; in tegra_nand_attach_chip()
946 if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN) { in tegra_nand_attach_chip()
947 if (mtd->writesize < 2048) in tegra_nand_attach_chip()
948 chip->ecc.algo = NAND_ECC_ALGO_RS; in tegra_nand_attach_chip()
950 chip->ecc.algo = NAND_ECC_ALGO_BCH; in tegra_nand_attach_chip()
953 if (chip->ecc.algo == NAND_ECC_ALGO_BCH && mtd->writesize < 2048) { in tegra_nand_attach_chip()
954 dev_err(ctrl->dev, "BCH supports 2K or 4K page size only\n"); in tegra_nand_attach_chip()
955 return -EINVAL; in tegra_nand_attach_chip()
958 if (!chip->ecc.strength) { in tegra_nand_attach_chip()
959 ret = tegra_nand_select_strength(chip, mtd->oobsize); in tegra_nand_attach_chip()
961 dev_err(ctrl->dev, in tegra_nand_attach_chip()
962 "No valid strength found, minimum %d\n", in tegra_nand_attach_chip()
963 requirements->strength); in tegra_nand_attach_chip()
967 chip->ecc.strength = ret; in tegra_nand_attach_chip()
970 nand->config_ecc = CONFIG_PIPE_EN | CONFIG_SKIP_SPARE | in tegra_nand_attach_chip()
973 switch (chip->ecc.algo) { in tegra_nand_attach_chip()
975 bits_per_step = BITS_PER_STEP_RS * chip->ecc.strength; in tegra_nand_attach_chip()
977 nand->config_ecc |= CONFIG_HW_ECC | CONFIG_ECC_SEL | in tegra_nand_attach_chip()
979 switch (chip->ecc.strength) { in tegra_nand_attach_chip()
981 nand->config_ecc |= CONFIG_TVAL_4; in tegra_nand_attach_chip()
984 nand->config_ecc |= CONFIG_TVAL_6; in tegra_nand_attach_chip()
987 nand->config_ecc |= CONFIG_TVAL_8; in tegra_nand_attach_chip()
990 dev_err(ctrl->dev, "ECC strength %d not supported\n", in tegra_nand_attach_chip()
991 chip->ecc.strength); in tegra_nand_attach_chip()
992 return -EINVAL; in tegra_nand_attach_chip()
996 bits_per_step = BITS_PER_STEP_BCH * chip->ecc.strength; in tegra_nand_attach_chip()
998 nand->bch_config = BCH_ENABLE; in tegra_nand_attach_chip()
999 switch (chip->ecc.strength) { in tegra_nand_attach_chip()
1001 nand->bch_config |= BCH_TVAL_4; in tegra_nand_attach_chip()
1004 nand->bch_config |= BCH_TVAL_8; in tegra_nand_attach_chip()
1007 nand->bch_config |= BCH_TVAL_14; in tegra_nand_attach_chip()
1010 nand->bch_config |= BCH_TVAL_16; in tegra_nand_attach_chip()
1013 dev_err(ctrl->dev, "ECC strength %d not supported\n", in tegra_nand_attach_chip()
1014 chip->ecc.strength); in tegra_nand_attach_chip()
1015 return -EINVAL; in tegra_nand_attach_chip()
1019 dev_err(ctrl->dev, "ECC algorithm not supported\n"); in tegra_nand_attach_chip()
1020 return -EINVAL; in tegra_nand_attach_chip()
1023 dev_info(ctrl->dev, "Using %s with strength %d per 512 byte step\n", in tegra_nand_attach_chip()
1024 chip->ecc.algo == NAND_ECC_ALGO_BCH ? "BCH" : "RS", in tegra_nand_attach_chip()
1025 chip->ecc.strength); in tegra_nand_attach_chip()
1027 chip->ecc.bytes = DIV_ROUND_UP(bits_per_step, BITS_PER_BYTE); in tegra_nand_attach_chip()
1029 switch (mtd->writesize) { in tegra_nand_attach_chip()
1031 nand->config |= CONFIG_PS_256; in tegra_nand_attach_chip()
1034 nand->config |= CONFIG_PS_512; in tegra_nand_attach_chip()
1037 nand->config |= CONFIG_PS_1024; in tegra_nand_attach_chip()
1040 nand->config |= CONFIG_PS_2048; in tegra_nand_attach_chip()
1043 nand->config |= CONFIG_PS_4096; in tegra_nand_attach_chip()
1046 dev_err(ctrl->dev, "Unsupported writesize %d\n", in tegra_nand_attach_chip()
1047 mtd->writesize); in tegra_nand_attach_chip()
1048 return -ENODEV; in tegra_nand_attach_chip()
1052 nand->config_ecc |= nand->config; in tegra_nand_attach_chip()
1054 /* Non-HW ECC read/writes complete OOB */ in tegra_nand_attach_chip()
1055 nand->config |= CONFIG_TAG_BYTE_SIZE(mtd->oobsize - 1); in tegra_nand_attach_chip()
1056 writel_relaxed(nand->config, ctrl->regs + CONFIG); in tegra_nand_attach_chip()
1070 struct device_node *np = dev->of_node; in tegra_nand_chips_init()
1081 return -EINVAL; in tegra_nand_chips_init()
1089 return -EINVAL; in tegra_nand_chips_init()
1101 return -ENOMEM; in tegra_nand_chips_init()
1103 nand->cs[0] = cs; in tegra_nand_chips_init()
1105 nand->wp_gpio = devm_gpiod_get_optional(dev, "wp", GPIOD_OUT_LOW); in tegra_nand_chips_init()
1107 if (IS_ERR(nand->wp_gpio)) { in tegra_nand_chips_init()
1108 ret = PTR_ERR(nand->wp_gpio); in tegra_nand_chips_init()
1113 chip = &nand->chip; in tegra_nand_chips_init()
1114 chip->controller = &ctrl->controller; in tegra_nand_chips_init()
1118 mtd->dev.parent = dev; in tegra_nand_chips_init()
1119 mtd->owner = THIS_MODULE; in tegra_nand_chips_init()
1123 if (!mtd->name) in tegra_nand_chips_init()
1124 mtd->name = "tegra_nand"; in tegra_nand_chips_init()
1126 chip->options = NAND_NO_SUBPAGE_WRITE | NAND_USES_DMA; in tegra_nand_chips_init()
1132 mtd_ooblayout_ecc(mtd, 0, &nand->ecc); in tegra_nand_chips_init()
1141 ctrl->chip = chip; in tegra_nand_chips_init()
1152 ctrl = devm_kzalloc(&pdev->dev, sizeof(*ctrl), GFP_KERNEL); in tegra_nand_probe()
1154 return -ENOMEM; in tegra_nand_probe()
1156 ctrl->dev = &pdev->dev; in tegra_nand_probe()
1158 nand_controller_init(&ctrl->controller); in tegra_nand_probe()
1159 ctrl->controller.ops = &tegra_nand_controller_ops; in tegra_nand_probe()
1161 ctrl->regs = devm_platform_ioremap_resource(pdev, 0); in tegra_nand_probe()
1162 if (IS_ERR(ctrl->regs)) in tegra_nand_probe()
1163 return PTR_ERR(ctrl->regs); in tegra_nand_probe()
1165 rst = devm_reset_control_get(&pdev->dev, "nand"); in tegra_nand_probe()
1169 ctrl->clk = devm_clk_get(&pdev->dev, "nand"); in tegra_nand_probe()
1170 if (IS_ERR(ctrl->clk)) in tegra_nand_probe()
1171 return PTR_ERR(ctrl->clk); in tegra_nand_probe()
1173 err = devm_tegra_core_dev_init_opp_table_common(&pdev->dev); in tegra_nand_probe()
1181 pm_runtime_enable(&pdev->dev); in tegra_nand_probe()
1182 err = pm_runtime_resume_and_get(&pdev->dev); in tegra_nand_probe()
1188 dev_err(ctrl->dev, "Failed to reset HW: %d\n", err); in tegra_nand_probe()
1192 writel_relaxed(HWSTATUS_CMD_DEFAULT, ctrl->regs + HWSTATUS_CMD); in tegra_nand_probe()
1193 writel_relaxed(HWSTATUS_MASK_DEFAULT, ctrl->regs + HWSTATUS_MASK); in tegra_nand_probe()
1194 writel_relaxed(INT_MASK, ctrl->regs + IER); in tegra_nand_probe()
1196 init_completion(&ctrl->command_complete); in tegra_nand_probe()
1197 init_completion(&ctrl->dma_complete); in tegra_nand_probe()
1199 ctrl->irq = platform_get_irq(pdev, 0); in tegra_nand_probe()
1200 if (ctrl->irq < 0) { in tegra_nand_probe()
1201 err = ctrl->irq; in tegra_nand_probe()
1204 err = devm_request_irq(&pdev->dev, ctrl->irq, tegra_nand_irq, 0, in tegra_nand_probe()
1205 dev_name(&pdev->dev), ctrl); in tegra_nand_probe()
1207 dev_err(ctrl->dev, "Failed to get IRQ: %d\n", err); in tegra_nand_probe()
1211 writel_relaxed(DMA_MST_CTRL_IS_DONE, ctrl->regs + DMA_MST_CTRL); in tegra_nand_probe()
1213 err = tegra_nand_chips_init(ctrl->dev, ctrl); in tegra_nand_probe()
1220 pm_runtime_put_sync_suspend(ctrl->dev); in tegra_nand_probe()
1221 pm_runtime_force_suspend(ctrl->dev); in tegra_nand_probe()
1223 pm_runtime_disable(&pdev->dev); in tegra_nand_probe()
1230 struct nand_chip *chip = ctrl->chip; in tegra_nand_remove()
1237 pm_runtime_put_sync_suspend(ctrl->dev); in tegra_nand_remove()
1238 pm_runtime_force_suspend(ctrl->dev); in tegra_nand_remove()
1246 err = clk_prepare_enable(ctrl->clk); in tegra_nand_runtime_resume()
1259 clk_disable_unprepare(ctrl->clk); in tegra_nand_runtime_suspend()
1270 { .compatible = "nvidia,tegra20-nand" },
1277 .name = "tegra-nand",