Lines Matching +full:x +full:- +full:max
1 // SPDX-License-Identifier: GPL-2.0
3 * Evatronix/Renesas R-Car Gen3, RZ/N1D, RZ/N1S, RZ/N1L NAND controller driver
11 #include <linux/dma-mapping.h>
23 #define COMMAND_SEQ(x) FIELD_PREP(GENMASK(5, 0), (x)) argument
36 #define COMMAND_0(x) FIELD_PREP(GENMASK(15, 8), (x)) argument
37 #define COMMAND_1(x) FIELD_PREP(GENMASK(23, 16), (x)) argument
38 #define COMMAND_2(x) FIELD_PREP(GENMASK(31, 24), (x)) argument
42 #define CONTROL_ECC_BLOCK_SIZE(x) FIELD_PREP(GENMASK(2, 1), (x)) argument
48 #define CONTROL_BLOCK_SIZE(x) FIELD_PREP(GENMASK(7, 6), (x)) argument
59 #define ECC_CTRL_CAP(x) FIELD_PREP(GENMASK(2, 0), (x)) argument
66 #define ECC_CTRL_ERR_THRESHOLD(x) FIELD_PREP(GENMASK(13, 8), (x)) argument
78 #define ECC_OFFSET(x) FIELD_PREP(GENMASK(15, 0), (x)) argument
85 #define ADDR0_COL(x) FIELD_PREP(GENMASK(15, 0), (x)) argument
88 #define ADDR0_ROW(x) FIELD_PREP(GENMASK(23, 0), (x)) argument
91 #define ADDR1_COL(x) FIELD_PREP(GENMASK(15, 0), (x)) argument
94 #define ADDR1_ROW(x) FIELD_PREP(GENMASK(23, 0), (x)) argument
118 #define DATA_SIZE(x) FIELD_PREP(GENMASK(14, 0), (x)) argument
121 #define TIMINGS_ASYN_TRWP(x) FIELD_PREP(GENMASK(3, 0), max((x), 1U) - 1) argument
122 #define TIMINGS_ASYN_TRWH(x) FIELD_PREP(GENMASK(7, 4), max((x), 1U) - 1) argument
125 #define TIM_SEQ0_TCCS(x) FIELD_PREP(GENMASK(5, 0), max((x), 1U) - 1) argument
126 #define TIM_SEQ0_TADL(x) FIELD_PREP(GENMASK(13, 8), max((x), 1U) - 1) argument
127 #define TIM_SEQ0_TRHW(x) FIELD_PREP(GENMASK(21, 16), max((x), 1U) - 1) argument
128 #define TIM_SEQ0_TWHR(x) FIELD_PREP(GENMASK(29, 24), max((x), 1U) - 1) argument
131 #define TIM_SEQ1_TWB(x) FIELD_PREP(GENMASK(5, 0), max((x), 1U) - 1) argument
132 #define TIM_SEQ1_TRR(x) FIELD_PREP(GENMASK(13, 8), max((x), 1U) - 1) argument
133 #define TIM_SEQ1_TWW(x) FIELD_PREP(GENMASK(21, 16), max((x), 1U) - 1) argument
136 #define TIM_GEN_SEQ0_D0(x) FIELD_PREP(GENMASK(5, 0), max((x), 1U) - 1) argument
137 #define TIM_GEN_SEQ0_D1(x) FIELD_PREP(GENMASK(13, 8), max((x), 1U) - 1) argument
138 #define TIM_GEN_SEQ0_D2(x) FIELD_PREP(GENMASK(21, 16), max((x), 1U) - 1) argument
139 #define TIM_GEN_SEQ0_D3(x) FIELD_PREP(GENMASK(29, 24), max((x), 1U) - 1) argument
142 #define TIM_GEN_SEQ1_D4(x) FIELD_PREP(GENMASK(5, 0), max((x), 1U) - 1) argument
143 #define TIM_GEN_SEQ1_D5(x) FIELD_PREP(GENMASK(13, 8), max((x), 1U) - 1) argument
144 #define TIM_GEN_SEQ1_D6(x) FIELD_PREP(GENMASK(21, 16), max((x), 1U) - 1) argument
145 #define TIM_GEN_SEQ1_D7(x) FIELD_PREP(GENMASK(29, 24), max((x), 1U) - 1) argument
148 #define TIM_GEN_SEQ2_D8(x) FIELD_PREP(GENMASK(5, 0), max((x), 1U) - 1) argument
149 #define TIM_GEN_SEQ2_D9(x) FIELD_PREP(GENMASK(13, 8), max((x), 1U) - 1) argument
150 #define TIM_GEN_SEQ2_D10(x) FIELD_PREP(GENMASK(21, 16), max((x), 1U) - 1) argument
151 #define TIM_GEN_SEQ2_D11(x) FIELD_PREP(GENMASK(29, 24), max((x), 1U) - 1) argument
168 #define GEN_SEQ_COL_A0(x) FIELD_PREP(GENMASK(5, 4), min((x), 2U)) argument
169 #define GEN_SEQ_COL_A1(x) FIELD_PREP(GENMASK(7, 6), min((x), 2U)) argument
170 #define GEN_SEQ_ROW_A0(x) FIELD_PREP(GENMASK(9, 8), min((x), 3U)) argument
171 #define GEN_SEQ_ROW_A1(x) FIELD_PREP(GENMASK(11, 10), min((x), 3U)) argument
173 #define GEN_SEQ_DELAY_EN(x) FIELD_PREP(GENMASK(14, 13), (x)) argument
177 #define GEN_SEQ_COMMAND_3(x) FIELD_PREP(GENMASK(26, 16), (x)) argument
180 #define DMA_TLVL(x) FIELD_PREP(GENMASK(7, 0), (x)) argument
184 #define TIM_GEN_SEQ3_D12(x) FIELD_PREP(GENMASK(5, 0), max((x), 1U) - 1) argument
256 return nand->sels[nand->selected_die].cs; in to_rnandc_cs()
263 control = readl_relaxed(rnandc->regs + CONTROL_REG); in rnandc_dis_correction()
265 writel_relaxed(control, rnandc->regs + CONTROL_REG); in rnandc_dis_correction()
272 control = readl_relaxed(rnandc->regs + CONTROL_REG); in rnandc_en_correction()
274 writel_relaxed(control, rnandc->regs + CONTROL_REG); in rnandc_en_correction()
279 writel_relaxed(0, rnandc->regs + INT_STATUS_REG); in rnandc_clear_status()
280 writel_relaxed(0, rnandc->regs + ECC_STAT_REG); in rnandc_clear_status()
281 writel_relaxed(0, rnandc->regs + ECC_CNT_REG); in rnandc_clear_status()
286 writel_relaxed(0, rnandc->regs + INT_MASK_REG); in rnandc_dis_interrupts()
291 if (!rnandc->use_polling) in rnandc_en_interrupts()
292 writel_relaxed(val, rnandc->regs + INT_MASK_REG); in rnandc_en_interrupts()
297 writel_relaxed(FIFO_INIT, rnandc->regs + FIFO_INIT_REG); in rnandc_clear_fifo()
303 struct rnandc *rnandc = to_rnandc(chip->controller); in rnandc_select_target()
304 unsigned int cs = rnand->sels[die_nr].cs; in rnandc_select_target()
306 if (chip == rnandc->selected_chip && die_nr == rnand->selected_die) in rnandc_select_target()
310 writel_relaxed(MEM_CTRL_CS(cs) | MEM_CTRL_DIS_WP(cs), rnandc->regs + MEM_CTRL_REG); in rnandc_select_target()
311 writel_relaxed(rnand->control, rnandc->regs + CONTROL_REG); in rnandc_select_target()
312 writel_relaxed(rnand->ecc_ctrl, rnandc->regs + ECC_CTRL_REG); in rnandc_select_target()
313 writel_relaxed(rnand->timings_asyn, rnandc->regs + TIMINGS_ASYN_REG); in rnandc_select_target()
314 writel_relaxed(rnand->tim_seq0, rnandc->regs + TIM_SEQ0_REG); in rnandc_select_target()
315 writel_relaxed(rnand->tim_seq1, rnandc->regs + TIM_SEQ1_REG); in rnandc_select_target()
316 writel_relaxed(rnand->tim_gen_seq0, rnandc->regs + TIM_GEN_SEQ0_REG); in rnandc_select_target()
317 writel_relaxed(rnand->tim_gen_seq1, rnandc->regs + TIM_GEN_SEQ1_REG); in rnandc_select_target()
318 writel_relaxed(rnand->tim_gen_seq2, rnandc->regs + TIM_GEN_SEQ2_REG); in rnandc_select_target()
319 writel_relaxed(rnand->tim_gen_seq3, rnandc->regs + TIM_GEN_SEQ3_REG); in rnandc_select_target()
321 rnandc->selected_chip = chip; in rnandc_select_target()
322 rnand->selected_die = die_nr; in rnandc_select_target()
327 writel_relaxed(rop->addr0_col, rnandc->regs + ADDR0_COL_REG); in rnandc_trigger_op()
328 writel_relaxed(rop->addr0_row, rnandc->regs + ADDR0_ROW_REG); in rnandc_trigger_op()
329 writel_relaxed(rop->addr1_col, rnandc->regs + ADDR1_COL_REG); in rnandc_trigger_op()
330 writel_relaxed(rop->addr1_row, rnandc->regs + ADDR1_ROW_REG); in rnandc_trigger_op()
331 writel_relaxed(rop->ecc_offset, rnandc->regs + ECC_OFFSET_REG); in rnandc_trigger_op()
332 writel_relaxed(rop->gen_seq_ctrl, rnandc->regs + GEN_SEQ_CTRL_REG); in rnandc_trigger_op()
333 writel_relaxed(DATA_SIZE(rop->len), rnandc->regs + DATA_SIZE_REG); in rnandc_trigger_op()
334 writel_relaxed(rop->command, rnandc->regs + COMMAND_REG); in rnandc_trigger_op()
341 DMA_CTRL_START, rnandc->regs + DMA_CTRL_REG); in rnandc_trigger_dma()
349 complete(&rnandc->complete); in rnandc_irq_handler()
362 ret = readl_poll_timeout(rnandc->regs + STATUS_REG, status, in rnandc_wait_end_of_op()
366 dev_err(rnandc->dev, "Operation timed out, status: 0x%08x\n", in rnandc_wait_end_of_op()
378 if (rnandc->use_polling) { in rnandc_wait_end_of_io()
383 ret = readl_poll_timeout(rnandc->regs + INT_STATUS_REG, status, in rnandc_wait_end_of_io()
388 ret = wait_for_completion_timeout(&rnandc->complete, in rnandc_wait_end_of_io()
391 ret = -ETIMEDOUT; in rnandc_wait_end_of_io()
402 struct rnandc *rnandc = to_rnandc(chip->controller); in rnandc_read_page_hw_ecc()
411 .len = mtd->writesize, in rnandc_read_page_hw_ecc()
412 .ecc_offset = ECC_OFFSET(mtd->writesize + 2), in rnandc_read_page_hw_ecc()
420 rnandc_select_target(chip, chip->cur_cs); in rnandc_read_page_hw_ecc()
422 reinit_completion(&rnandc->complete); in rnandc_read_page_hw_ecc()
427 dma_addr = dma_map_single(rnandc->dev, rnandc->buf, mtd->writesize, in rnandc_read_page_hw_ecc()
429 writel(dma_addr, rnandc->regs + DMA_ADDR_LOW_REG); in rnandc_read_page_hw_ecc()
430 writel(mtd->writesize, rnandc->regs + DMA_CNT_REG); in rnandc_read_page_hw_ecc()
431 writel(DMA_TLVL_MAX, rnandc->regs + DMA_TLVL_REG); in rnandc_read_page_hw_ecc()
437 dma_unmap_single(rnandc->dev, dma_addr, mtd->writesize, DMA_FROM_DEVICE); in rnandc_read_page_hw_ecc()
440 dev_err(rnandc->dev, "Read page operation never ending\n"); in rnandc_read_page_hw_ecc()
444 ecc_stat = readl_relaxed(rnandc->regs + ECC_STAT_REG); in rnandc_read_page_hw_ecc()
447 ret = nand_change_read_column_op(chip, mtd->writesize, in rnandc_read_page_hw_ecc()
448 chip->oob_poi, mtd->oobsize, in rnandc_read_page_hw_ecc()
455 for (i = 0; i < chip->ecc.steps; i++) { in rnandc_read_page_hw_ecc()
456 unsigned int off = i * chip->ecc.size; in rnandc_read_page_hw_ecc()
457 unsigned int eccoff = i * chip->ecc.bytes; in rnandc_read_page_hw_ecc()
459 bf = nand_check_erased_ecc_chunk(rnandc->buf + off, in rnandc_read_page_hw_ecc()
460 chip->ecc.size, in rnandc_read_page_hw_ecc()
461 chip->oob_poi + 2 + eccoff, in rnandc_read_page_hw_ecc()
462 chip->ecc.bytes, in rnandc_read_page_hw_ecc()
464 chip->ecc.strength); in rnandc_read_page_hw_ecc()
466 mtd->ecc_stats.failed++; in rnandc_read_page_hw_ecc()
468 mtd->ecc_stats.corrected += bf; in rnandc_read_page_hw_ecc()
473 bf = ECC_CNT(cs, readl_relaxed(rnandc->regs + ECC_CNT_REG)); in rnandc_read_page_hw_ecc()
476 * that this controller does not provide per-chunk details but in rnandc_read_page_hw_ecc()
479 mtd->ecc_stats.corrected += bf; in rnandc_read_page_hw_ecc()
482 memcpy(buf, rnandc->buf, mtd->writesize); in rnandc_read_page_hw_ecc()
490 struct rnandc *rnandc = to_rnandc(chip->controller); in rnandc_read_subpage_hw_ecc()
494 unsigned int page_off = round_down(req_offset, chip->ecc.size); in rnandc_read_subpage_hw_ecc()
495 unsigned int real_len = round_up(req_offset + req_len - page_off, in rnandc_read_subpage_hw_ecc()
496 chip->ecc.size); in rnandc_read_subpage_hw_ecc()
497 unsigned int start_chunk = page_off / chip->ecc.size; in rnandc_read_subpage_hw_ecc()
498 unsigned int nchunks = real_len / chip->ecc.size; in rnandc_read_subpage_hw_ecc()
499 unsigned int ecc_off = 2 + (start_chunk * chip->ecc.bytes); in rnandc_read_subpage_hw_ecc()
507 .ecc_offset = ECC_OFFSET(mtd->writesize + ecc_off), in rnandc_read_subpage_hw_ecc()
514 rnandc_select_target(chip, chip->cur_cs); in rnandc_read_subpage_hw_ecc()
519 while (!FIFO_STATE_C_EMPTY(readl(rnandc->regs + FIFO_STATE_REG))) in rnandc_read_subpage_hw_ecc()
522 while (FIFO_STATE_R_EMPTY(readl(rnandc->regs + FIFO_STATE_REG))) in rnandc_read_subpage_hw_ecc()
525 ioread32_rep(rnandc->regs + FIFO_DATA_REG, bufpoi + page_off, in rnandc_read_subpage_hw_ecc()
528 if (!FIFO_STATE_R_EMPTY(readl(rnandc->regs + FIFO_STATE_REG))) { in rnandc_read_subpage_hw_ecc()
529 dev_err(rnandc->dev, "Clearing residual data in the read FIFO\n"); in rnandc_read_subpage_hw_ecc()
536 dev_err(rnandc->dev, "Read subpage operation never ending\n"); in rnandc_read_subpage_hw_ecc()
540 ecc_stat = readl_relaxed(rnandc->regs + ECC_STAT_REG); in rnandc_read_subpage_hw_ecc()
543 ret = nand_change_read_column_op(chip, mtd->writesize, in rnandc_read_subpage_hw_ecc()
544 chip->oob_poi, mtd->oobsize, in rnandc_read_subpage_hw_ecc()
550 unsigned int dataoff = i * chip->ecc.size; in rnandc_read_subpage_hw_ecc()
551 unsigned int eccoff = 2 + (i * chip->ecc.bytes); in rnandc_read_subpage_hw_ecc()
554 chip->ecc.size, in rnandc_read_subpage_hw_ecc()
555 chip->oob_poi + eccoff, in rnandc_read_subpage_hw_ecc()
556 chip->ecc.bytes, in rnandc_read_subpage_hw_ecc()
558 chip->ecc.strength); in rnandc_read_subpage_hw_ecc()
560 mtd->ecc_stats.failed++; in rnandc_read_subpage_hw_ecc()
562 mtd->ecc_stats.corrected += bf; in rnandc_read_subpage_hw_ecc()
567 bf = ECC_CNT(cs, readl_relaxed(rnandc->regs + ECC_CNT_REG)); in rnandc_read_subpage_hw_ecc()
570 * that this controller does not provide per-chunk details but in rnandc_read_subpage_hw_ecc()
573 mtd->ecc_stats.corrected += bf; in rnandc_read_subpage_hw_ecc()
582 struct rnandc *rnandc = to_rnandc(chip->controller); in rnandc_write_page_hw_ecc()
591 .len = mtd->writesize, in rnandc_write_page_hw_ecc()
592 .ecc_offset = ECC_OFFSET(mtd->writesize + 2), in rnandc_write_page_hw_ecc()
597 memcpy(rnandc->buf, buf, mtd->writesize); in rnandc_write_page_hw_ecc()
600 rnandc_select_target(chip, chip->cur_cs); in rnandc_write_page_hw_ecc()
602 reinit_completion(&rnandc->complete); in rnandc_write_page_hw_ecc()
607 dma_addr = dma_map_single(rnandc->dev, (void *)rnandc->buf, mtd->writesize, in rnandc_write_page_hw_ecc()
609 writel(dma_addr, rnandc->regs + DMA_ADDR_LOW_REG); in rnandc_write_page_hw_ecc()
610 writel(mtd->writesize, rnandc->regs + DMA_CNT_REG); in rnandc_write_page_hw_ecc()
611 writel(DMA_TLVL_MAX, rnandc->regs + DMA_TLVL_REG); in rnandc_write_page_hw_ecc()
617 dma_unmap_single(rnandc->dev, dma_addr, mtd->writesize, DMA_TO_DEVICE); in rnandc_write_page_hw_ecc()
620 dev_err(rnandc->dev, "Write page operation never ending\n"); in rnandc_write_page_hw_ecc()
627 return nand_change_write_column_op(chip, mtd->writesize, chip->oob_poi, in rnandc_write_page_hw_ecc()
628 mtd->oobsize, false); in rnandc_write_page_hw_ecc()
635 struct rnandc *rnandc = to_rnandc(chip->controller); in rnandc_write_subpage_hw_ecc()
637 unsigned int page_off = round_down(req_offset, chip->ecc.size); in rnandc_write_subpage_hw_ecc()
638 unsigned int real_len = round_up(req_offset + req_len - page_off, in rnandc_write_subpage_hw_ecc()
639 chip->ecc.size); in rnandc_write_subpage_hw_ecc()
640 unsigned int start_chunk = page_off / chip->ecc.size; in rnandc_write_subpage_hw_ecc()
641 unsigned int ecc_off = 2 + (start_chunk * chip->ecc.bytes); in rnandc_write_subpage_hw_ecc()
649 .ecc_offset = ECC_OFFSET(mtd->writesize + ecc_off), in rnandc_write_subpage_hw_ecc()
654 rnandc_select_target(chip, chip->cur_cs); in rnandc_write_subpage_hw_ecc()
659 while (FIFO_STATE_W_FULL(readl(rnandc->regs + FIFO_STATE_REG))) in rnandc_write_subpage_hw_ecc()
662 iowrite32_rep(rnandc->regs + FIFO_DATA_REG, bufpoi + page_off, in rnandc_write_subpage_hw_ecc()
665 while (!FIFO_STATE_W_EMPTY(readl(rnandc->regs + FIFO_STATE_REG))) in rnandc_write_subpage_hw_ecc()
671 dev_err(rnandc->dev, "Write subpage operation never ending\n"); in rnandc_write_subpage_hw_ecc()
685 struct rnandc *rnandc = to_rnandc(chip->controller); in rnandc_exec_op()
699 rnandc_select_target(chip, op->cs); in rnandc_exec_op()
701 for (op_id = 0; op_id < op->ninstrs; op_id++) { in rnandc_exec_op()
702 instr = &op->instrs[op_id]; in rnandc_exec_op()
706 switch (instr->type) { in rnandc_exec_op()
710 rop.command |= COMMAND_0(instr->ctx.cmd.opcode); in rnandc_exec_op()
714 rop.gen_seq_ctrl |= GEN_SEQ_COMMAND_3(instr->ctx.cmd.opcode); in rnandc_exec_op()
720 rop.command |= COMMAND_2(instr->ctx.cmd.opcode); in rnandc_exec_op()
726 rop.command |= COMMAND_1(instr->ctx.cmd.opcode); in rnandc_exec_op()
736 return -EOPNOTSUPP; in rnandc_exec_op()
741 addrs = instr->ctx.addr.addrs; in rnandc_exec_op()
742 naddrs = instr->ctx.addr.naddrs; in rnandc_exec_op()
744 return -EOPNOTSUPP; in rnandc_exec_op()
747 row_addrs = naddrs > 2 ? naddrs - col_addrs : 0; in rnandc_exec_op()
775 return -EOPNOTSUPP; in rnandc_exec_op()
784 rop.buf = instr->ctx.data.buf.in; in rnandc_exec_op()
785 rop.len = instr->ctx.data.len; in rnandc_exec_op()
798 return -EOPNOTSUPP; in rnandc_exec_op()
819 return -EOPNOTSUPP; in rnandc_exec_op()
835 dev_err(rnandc->dev, "Cannot handle more than one wait delay\n"); in rnandc_exec_op()
836 return -EOPNOTSUPP; in rnandc_exec_op()
847 while (!FIFO_STATE_C_EMPTY(readl(rnandc->regs + FIFO_STATE_REG))) in rnandc_exec_op()
850 while (FIFO_STATE_R_EMPTY(readl(rnandc->regs + FIFO_STATE_REG))) in rnandc_exec_op()
853 ioread32_rep(rnandc->regs + FIFO_DATA_REG, rop.buf, words); in rnandc_exec_op()
855 last_bytes = readl_relaxed(rnandc->regs + FIFO_DATA_REG); in rnandc_exec_op()
860 if (!FIFO_STATE_R_EMPTY(readl(rnandc->regs + FIFO_STATE_REG))) { in rnandc_exec_op()
861 dev_warn(rnandc->dev, in rnandc_exec_op()
866 while (FIFO_STATE_W_FULL(readl(rnandc->regs + FIFO_STATE_REG))) in rnandc_exec_op()
869 iowrite32_rep(rnandc->regs + FIFO_DATA_REG, rop.buf, in rnandc_exec_op()
875 writel_relaxed(last_bytes, rnandc->regs + FIFO_DATA_REG); in rnandc_exec_op()
878 while (!FIFO_STATE_W_EMPTY(readl(rnandc->regs + FIFO_STATE_REG))) in rnandc_exec_op()
893 struct rnandc *rnandc = to_rnandc(chip->controller); in rnandc_setup_interface()
894 unsigned int period_ns = 1000000000 / rnandc->ext_clk_rate; in rnandc_setup_interface()
902 if (sdr->tRP_min != sdr->tWP_min || sdr->tREH_min != sdr->tWH_min) { in rnandc_setup_interface()
903 dev_err(rnandc->dev, "Read and write hold times must be identical\n"); in rnandc_setup_interface()
904 return -EINVAL; in rnandc_setup_interface()
910 rnand->timings_asyn = in rnandc_setup_interface()
911 TIMINGS_ASYN_TRWP(TO_CYCLES64(sdr->tRP_min, period_ns)) | in rnandc_setup_interface()
912 TIMINGS_ASYN_TRWH(TO_CYCLES64(sdr->tREH_min, period_ns)); in rnandc_setup_interface()
913 rnand->tim_seq0 = in rnandc_setup_interface()
914 TIM_SEQ0_TCCS(TO_CYCLES64(sdr->tCCS_min, period_ns)) | in rnandc_setup_interface()
915 TIM_SEQ0_TADL(TO_CYCLES64(sdr->tADL_min, period_ns)) | in rnandc_setup_interface()
916 TIM_SEQ0_TRHW(TO_CYCLES64(sdr->tRHW_min, period_ns)) | in rnandc_setup_interface()
917 TIM_SEQ0_TWHR(TO_CYCLES64(sdr->tWHR_min, period_ns)); in rnandc_setup_interface()
918 rnand->tim_seq1 = in rnandc_setup_interface()
919 TIM_SEQ1_TWB(TO_CYCLES64(sdr->tWB_max, period_ns)) | in rnandc_setup_interface()
920 TIM_SEQ1_TRR(TO_CYCLES64(sdr->tRR_min, period_ns)) | in rnandc_setup_interface()
921 TIM_SEQ1_TWW(TO_CYCLES64(sdr->tWW_min, period_ns)); in rnandc_setup_interface()
923 cyc = sdr->tDS_min + sdr->tDH_min; in rnandc_setup_interface()
924 cle = sdr->tCLH_min + sdr->tCLS_min; in rnandc_setup_interface()
925 ale = sdr->tALH_min + sdr->tALS_min; in rnandc_setup_interface()
926 bef_dly = sdr->tWB_max - sdr->tDH_min; in rnandc_setup_interface()
927 ca_to_data = sdr->tWHR_min + sdr->tREA_max - sdr->tDH_min; in rnandc_setup_interface()
930 * D0 = CMD -> ADDR = tCLH + tCLS - 1 cycle in rnandc_setup_interface()
931 * D1 = CMD -> CMD = tCLH + tCLS - 1 cycle in rnandc_setup_interface()
932 * D2 = CMD -> DLY = tWB - tDH in rnandc_setup_interface()
933 * D3 = CMD -> DATA = tWHR + tREA - tDH in rnandc_setup_interface()
935 rnand->tim_gen_seq0 = in rnandc_setup_interface()
936 TIM_GEN_SEQ0_D0(TO_CYCLES64(cle - cyc, period_ns)) | in rnandc_setup_interface()
937 TIM_GEN_SEQ0_D1(TO_CYCLES64(cle - cyc, period_ns)) | in rnandc_setup_interface()
942 * D4 = ADDR -> CMD = tALH + tALS - 1 cyle in rnandc_setup_interface()
943 * D5 = ADDR -> ADDR = tALH + tALS - 1 cyle in rnandc_setup_interface()
944 * D6 = ADDR -> DLY = tWB - tDH in rnandc_setup_interface()
945 * D7 = ADDR -> DATA = tWHR + tREA - tDH in rnandc_setup_interface()
947 rnand->tim_gen_seq1 = in rnandc_setup_interface()
948 TIM_GEN_SEQ1_D4(TO_CYCLES64(ale - cyc, period_ns)) | in rnandc_setup_interface()
949 TIM_GEN_SEQ1_D5(TO_CYCLES64(ale - cyc, period_ns)) | in rnandc_setup_interface()
954 * D8 = DLY -> DATA = tRR + tREA in rnandc_setup_interface()
955 * D9 = DLY -> CMD = tRR in rnandc_setup_interface()
956 * D10 = DATA -> CMD = tCLH + tCLS - 1 cycle in rnandc_setup_interface()
957 * D11 = DATA -> DLY = tWB - tDH in rnandc_setup_interface()
959 rnand->tim_gen_seq2 = in rnandc_setup_interface()
960 TIM_GEN_SEQ2_D8(TO_CYCLES64(sdr->tRR_min + sdr->tREA_max, period_ns)) | in rnandc_setup_interface()
961 TIM_GEN_SEQ2_D9(TO_CYCLES64(sdr->tRR_min, period_ns)) | in rnandc_setup_interface()
962 TIM_GEN_SEQ2_D10(TO_CYCLES64(cle - cyc, period_ns)) | in rnandc_setup_interface()
965 /* D12 = DATA -> END = tCLH - tDH */ in rnandc_setup_interface()
966 rnand->tim_gen_seq3 = in rnandc_setup_interface()
967 TIM_GEN_SEQ3_D12(TO_CYCLES64(sdr->tCLH_min - sdr->tDH_min, period_ns)); in rnandc_setup_interface()
976 unsigned int eccbytes = round_up(chip->ecc.bytes, 4) * chip->ecc.steps; in rnandc_ooblayout_ecc()
979 return -ERANGE; in rnandc_ooblayout_ecc()
981 oobregion->offset = 2; in rnandc_ooblayout_ecc()
982 oobregion->length = eccbytes; in rnandc_ooblayout_ecc()
991 unsigned int eccbytes = round_up(chip->ecc.bytes, 4) * chip->ecc.steps; in rnandc_ooblayout_free()
994 return -ERANGE; in rnandc_ooblayout_free()
996 oobregion->offset = 2 + eccbytes; in rnandc_ooblayout_free()
997 oobregion->length = mtd->oobsize - oobregion->offset; in rnandc_ooblayout_free()
1011 struct rnandc *rnandc = to_rnandc(chip->controller); in rnandc_hw_ecc_controller_init()
1013 if (mtd->writesize > SZ_16K) { in rnandc_hw_ecc_controller_init()
1014 dev_err(rnandc->dev, "Unsupported page size\n"); in rnandc_hw_ecc_controller_init()
1015 return -EINVAL; in rnandc_hw_ecc_controller_init()
1018 switch (chip->ecc.size) { in rnandc_hw_ecc_controller_init()
1020 rnand->control |= CONTROL_ECC_BLOCK_SIZE_256; in rnandc_hw_ecc_controller_init()
1023 rnand->control |= CONTROL_ECC_BLOCK_SIZE_512; in rnandc_hw_ecc_controller_init()
1026 rnand->control |= CONTROL_ECC_BLOCK_SIZE_1024; in rnandc_hw_ecc_controller_init()
1029 dev_err(rnandc->dev, "Unsupported ECC chunk size\n"); in rnandc_hw_ecc_controller_init()
1030 return -EINVAL; in rnandc_hw_ecc_controller_init()
1033 switch (chip->ecc.strength) { in rnandc_hw_ecc_controller_init()
1035 chip->ecc.bytes = 4; in rnandc_hw_ecc_controller_init()
1036 rnand->ecc_ctrl |= ECC_CTRL_CAP_2B; in rnandc_hw_ecc_controller_init()
1039 chip->ecc.bytes = 7; in rnandc_hw_ecc_controller_init()
1040 rnand->ecc_ctrl |= ECC_CTRL_CAP_4B; in rnandc_hw_ecc_controller_init()
1043 chip->ecc.bytes = 14; in rnandc_hw_ecc_controller_init()
1044 rnand->ecc_ctrl |= ECC_CTRL_CAP_8B; in rnandc_hw_ecc_controller_init()
1047 chip->ecc.bytes = 28; in rnandc_hw_ecc_controller_init()
1048 rnand->ecc_ctrl |= ECC_CTRL_CAP_16B; in rnandc_hw_ecc_controller_init()
1051 chip->ecc.bytes = 42; in rnandc_hw_ecc_controller_init()
1052 rnand->ecc_ctrl |= ECC_CTRL_CAP_24B; in rnandc_hw_ecc_controller_init()
1055 chip->ecc.bytes = 56; in rnandc_hw_ecc_controller_init()
1056 rnand->ecc_ctrl |= ECC_CTRL_CAP_32B; in rnandc_hw_ecc_controller_init()
1059 dev_err(rnandc->dev, "Unsupported ECC strength\n"); in rnandc_hw_ecc_controller_init()
1060 return -EINVAL; in rnandc_hw_ecc_controller_init()
1063 rnand->ecc_ctrl |= ECC_CTRL_ERR_THRESHOLD(chip->ecc.strength); in rnandc_hw_ecc_controller_init()
1066 chip->ecc.steps = mtd->writesize / chip->ecc.size; in rnandc_hw_ecc_controller_init()
1067 chip->ecc.read_page = rnandc_read_page_hw_ecc; in rnandc_hw_ecc_controller_init()
1068 chip->ecc.read_subpage = rnandc_read_subpage_hw_ecc; in rnandc_hw_ecc_controller_init()
1069 chip->ecc.write_page = rnandc_write_page_hw_ecc; in rnandc_hw_ecc_controller_init()
1070 chip->ecc.write_subpage = rnandc_write_subpage_hw_ecc; in rnandc_hw_ecc_controller_init()
1077 struct nand_ecc_ctrl *ecc = &chip->ecc; in rnandc_ecc_init()
1079 nanddev_get_ecc_requirements(&chip->base); in rnandc_ecc_init()
1080 struct rnandc *rnandc = to_rnandc(chip->controller); in rnandc_ecc_init()
1083 if (ecc->engine_type != NAND_ECC_ENGINE_TYPE_NONE && in rnandc_ecc_init()
1084 (!ecc->size || !ecc->strength)) { in rnandc_ecc_init()
1085 if (requirements->step_size && requirements->strength) { in rnandc_ecc_init()
1086 ecc->size = requirements->step_size; in rnandc_ecc_init()
1087 ecc->strength = requirements->strength; in rnandc_ecc_init()
1089 dev_err(rnandc->dev, "No minimum ECC strength\n"); in rnandc_ecc_init()
1090 return -EINVAL; in rnandc_ecc_init()
1094 switch (ecc->engine_type) { in rnandc_ecc_init()
1105 return -EINVAL; in rnandc_ecc_init()
1114 struct rnandc *rnandc = to_rnandc(chip->controller); in rnandc_attach_chip()
1116 struct nand_memory_organization *memorg = nanddev_get_memorg(&chip->base); in rnandc_attach_chip()
1120 if (chip->bbt_options & NAND_BBT_USE_FLASH) in rnandc_attach_chip()
1121 chip->bbt_options |= NAND_BBT_NO_OOB; in rnandc_attach_chip()
1123 if (mtd->writesize <= 512) { in rnandc_attach_chip()
1124 dev_err(rnandc->dev, "Small page devices not supported\n"); in rnandc_attach_chip()
1125 return -EINVAL; in rnandc_attach_chip()
1128 rnand->control |= CONTROL_CHECK_RB_LINE | CONTROL_INT_EN; in rnandc_attach_chip()
1130 switch (memorg->pages_per_eraseblock) { in rnandc_attach_chip()
1132 rnand->control |= CONTROL_BLOCK_SIZE_32P; in rnandc_attach_chip()
1135 rnand->control |= CONTROL_BLOCK_SIZE_64P; in rnandc_attach_chip()
1138 rnand->control |= CONTROL_BLOCK_SIZE_128P; in rnandc_attach_chip()
1141 rnand->control |= CONTROL_BLOCK_SIZE_256P; in rnandc_attach_chip()
1144 dev_err(rnandc->dev, "Unsupported memory organization\n"); in rnandc_attach_chip()
1145 return -EINVAL; in rnandc_attach_chip()
1148 chip->options |= NAND_SUBPAGE_READ; in rnandc_attach_chip()
1152 dev_err(rnandc->dev, "ECC initialization failed (%d)\n", ret); in rnandc_attach_chip()
1157 rnand->selected_die = -1; in rnandc_attach_chip()
1171 unsigned int max_len = new_mtd->writesize + new_mtd->oobsize; in rnandc_alloc_dma_buf()
1176 list_for_each_entry_safe(entry, temp, &rnandc->chips, node) { in rnandc_alloc_dma_buf()
1177 chip = &entry->chip; in rnandc_alloc_dma_buf()
1179 max_len = max(max_len, mtd->writesize + mtd->oobsize); in rnandc_alloc_dma_buf()
1182 if (rnandc->buf && rnandc->buf_sz < max_len) { in rnandc_alloc_dma_buf()
1183 devm_kfree(rnandc->dev, rnandc->buf); in rnandc_alloc_dma_buf()
1184 rnandc->buf = NULL; in rnandc_alloc_dma_buf()
1187 if (!rnandc->buf) { in rnandc_alloc_dma_buf()
1188 rnandc->buf_sz = max_len; in rnandc_alloc_dma_buf()
1189 rnandc->buf = devm_kmalloc(rnandc->dev, max_len, in rnandc_alloc_dma_buf()
1191 if (!rnandc->buf) in rnandc_alloc_dma_buf()
1192 return -ENOMEM; in rnandc_alloc_dma_buf()
1208 ret = (nsels < 0) ? nsels : -EINVAL; in rnandc_chip_init()
1209 dev_err(rnandc->dev, "Invalid reg property (%d)\n", ret); in rnandc_chip_init()
1214 rnand = devm_kzalloc(rnandc->dev, struct_size(rnand, sels, nsels), in rnandc_chip_init()
1217 return -ENOMEM; in rnandc_chip_init()
1219 rnand->nsels = nsels; in rnandc_chip_init()
1220 rnand->selected_die = -1; in rnandc_chip_init()
1225 dev_err(rnandc->dev, "Incomplete reg property (%d)\n", ret); in rnandc_chip_init()
1230 dev_err(rnandc->dev, "Invalid reg property (%d)\n", cs); in rnandc_chip_init()
1231 return -EINVAL; in rnandc_chip_init()
1234 if (test_and_set_bit(cs, &rnandc->assigned_cs)) { in rnandc_chip_init()
1235 dev_err(rnandc->dev, "CS %d already assigned\n", cs); in rnandc_chip_init()
1236 return -EINVAL; in rnandc_chip_init()
1243 rnand->sels[i].cs = cs; in rnandc_chip_init()
1246 chip = &rnand->chip; in rnandc_chip_init()
1247 chip->controller = &rnandc->controller; in rnandc_chip_init()
1251 mtd->dev.parent = rnandc->dev; in rnandc_chip_init()
1252 if (!mtd->name) { in rnandc_chip_init()
1253 dev_err(rnandc->dev, "Missing MTD label\n"); in rnandc_chip_init()
1254 return -EINVAL; in rnandc_chip_init()
1257 ret = nand_scan(chip, rnand->nsels); in rnandc_chip_init()
1259 dev_err(rnandc->dev, "Failed to scan the NAND chip (%d)\n", ret); in rnandc_chip_init()
1269 dev_err(rnandc->dev, "Failed to register MTD device (%d)\n", ret); in rnandc_chip_init()
1273 list_add_tail(&rnand->node, &rnandc->chips); in rnandc_chip_init()
1289 list_for_each_entry_safe(entry, temp, &rnandc->chips, node) { in rnandc_chips_cleanup()
1290 chip = &entry->chip; in rnandc_chips_cleanup()
1294 list_del(&entry->node); in rnandc_chips_cleanup()
1302 for_each_child_of_node_scoped(rnandc->dev->of_node, np) { in rnandc_chips_init()
1319 rnandc = devm_kzalloc(&pdev->dev, sizeof(*rnandc), GFP_KERNEL); in rnandc_probe()
1321 return -ENOMEM; in rnandc_probe()
1323 rnandc->dev = &pdev->dev; in rnandc_probe()
1324 nand_controller_init(&rnandc->controller); in rnandc_probe()
1325 rnandc->controller.ops = &rnandc_ops; in rnandc_probe()
1326 INIT_LIST_HEAD(&rnandc->chips); in rnandc_probe()
1327 init_completion(&rnandc->complete); in rnandc_probe()
1329 rnandc->regs = devm_platform_ioremap_resource(pdev, 0); in rnandc_probe()
1330 if (IS_ERR(rnandc->regs)) in rnandc_probe()
1331 return PTR_ERR(rnandc->regs); in rnandc_probe()
1333 devm_pm_runtime_enable(&pdev->dev); in rnandc_probe()
1334 ret = pm_runtime_resume_and_get(&pdev->dev); in rnandc_probe()
1339 eclk = clk_get(&pdev->dev, "eclk"); in rnandc_probe()
1345 rnandc->ext_clk_rate = clk_get_rate(eclk); in rnandc_probe()
1350 if (irq == -EPROBE_DEFER) { in rnandc_probe()
1354 dev_info(&pdev->dev, "No IRQ found, fallback to polling\n"); in rnandc_probe()
1355 rnandc->use_polling = true; in rnandc_probe()
1357 ret = devm_request_irq(&pdev->dev, irq, rnandc_irq_handler, 0, in rnandc_probe()
1358 "renesas-nand-controller", rnandc); in rnandc_probe()
1363 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); in rnandc_probe()
1378 pm_runtime_put(&pdev->dev); in rnandc_probe()
1389 pm_runtime_put(&pdev->dev); in rnandc_remove()
1393 { .compatible = "renesas,rcar-gen3-nandc" },
1394 { .compatible = "renesas,rzn1-nandc" },
1401 .name = "renesas-nandc",
1410 MODULE_DESCRIPTION("Renesas R-Car Gen3 & RZ/N1 NAND controller driver");