nand/raw/r852.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  * Copyright © 2009 - Maxim Levitsky
15    byte write/read does one cycle on nand data lines.
16    dword write/read does 4 cycles
18    results of ecc correction, if DMA read was done before.
19    If write was done two dword reads read generated ecc checksums
26 #define R852_CTL_DATA		0x02	/* read/write data (#ALE)*/
30 #define R852_CTL_CARDENABLE	0x10	/* probably (#CE) - always set*/
32 #define R852_CTL_ECC_ACCESS	0x40	/* read/write ecc via reg #0*/
42 #define R852_CARD_STA_BUSY	0x80	/* card is busy - (#R/B) */
63 /* dma capabilities */
67 #define R852_DMA1		0x40	/* if set w/bit #7, dma is supported */
68 #define R852_DMA2		0x80	/* if set w/bit #6, dma is supported */
71 /* physical DMA address - 32 bit value*/
75 /* dma settings */
77 #define R852_DMA_MEMORY		0x01	/* (memory <-> internal hw buffer) */
78 #define R852_DMA_READ		0x02	/* 0 = write, 1 = read */
79 #define R852_DMA_INTERNAL	0x04	/* (internal hw buffer <-> card) */
81 /* dma IRQ status */
84 /* dma IRQ enable */
87 #define R852_DMA_IRQ_MEMORY	0x01	/* (memory <-> internal hw buffer) */
89 #define R852_DMA_IRQ_INTERNAL	0x04	/* (internal hw buffer <-> card) */
93 /* ECC syndrome format - read from reg #0 will return two copies of these for
97 #define R852_ECC_CORRECT		0x10	/* no errors - (guessed) */
112 	/* dma area */
119 	int dma_dir;			/* 1 = read, 0 = write */
120 	int dma_stage;			/* 0 - idle, 1 - first step,
121 					   2 - second step */
124 	int dma_error;			/* dma errors */
125 	int dma_usable;			/* is it possible to use dma */