193 nandc_set_reg(chip, reg,			\
199 nandc_set_reg(chip, reg,			\
751 static void nandc_set_reg(struct nand_chip *chip, int offset,  in nandc_set_reg()  function
799 	nandc_set_reg(chip, NAND_ADDR0, page << 16 | column);  in set_address()
800 	nandc_set_reg(chip, NAND_ADDR1, page >> 16 & 0xff);  in set_address()
840 	nandc_set_reg(chip, NAND_FLASH_CMD, cmd);  in update_rw_regs()
841 	nandc_set_reg(chip, NAND_DEV0_CFG0, cfg0);  in update_rw_regs()
842 	nandc_set_reg(chip, NAND_DEV0_CFG1, cfg1);  in update_rw_regs()
843 	nandc_set_reg(chip, NAND_DEV0_ECC_CFG, ecc_bch_cfg);  in update_rw_regs()
845 		nandc_set_reg(chip, NAND_EBI2_ECC_BUF_CFG, host->ecc_buf_cfg);  in update_rw_regs()
846 	nandc_set_reg(chip, NAND_FLASH_STATUS, host->clrflashstatus);  in update_rw_regs()
847 	nandc_set_reg(chip, NAND_READ_STATUS, host->clrreadstatus);  in update_rw_regs()
848 	nandc_set_reg(chip, NAND_EXEC_CMD, 1);  in update_rw_regs()
2709 	nandc_set_reg(chip, NAND_FLASH_CMD, q_op.cmd_reg);  in qcom_read_status_exec()
2710 	nandc_set_reg(chip, NAND_EXEC_CMD, 1);  in qcom_read_status_exec()
2766 	nandc_set_reg(chip, NAND_FLASH_CMD, q_op.cmd_reg);  in qcom_read_id_type_exec()
2767 	nandc_set_reg(chip, NAND_ADDR0, q_op.addr1_reg);  in qcom_read_id_type_exec()
2768 	nandc_set_reg(chip, NAND_ADDR1, q_op.addr2_reg);  in qcom_read_id_type_exec()
2769 	nandc_set_reg(chip, NAND_FLASH_CHIP_SELECT,  in qcom_read_id_type_exec()
2772 	nandc_set_reg(chip, NAND_EXEC_CMD, 1);  in qcom_read_id_type_exec()
2812 		nandc_set_reg(chip, NAND_ADDR0, q_op.addr1_reg);  in qcom_misc_cmd_type_exec()
2813 		nandc_set_reg(chip, NAND_ADDR1, q_op.addr2_reg);  in qcom_misc_cmd_type_exec()
2814 		nandc_set_reg(chip, NAND_DEV0_CFG0,  in qcom_misc_cmd_type_exec()
2816 		nandc_set_reg(chip, NAND_DEV0_CFG1, host->cfg1_raw);  in qcom_misc_cmd_type_exec()
2829 	nandc_set_reg(chip, NAND_FLASH_CMD, q_op.cmd_reg);  in qcom_misc_cmd_type_exec()
2830 	nandc_set_reg(chip, NAND_EXEC_CMD, 1);  in qcom_misc_cmd_type_exec()
2875 	nandc_set_reg(chip, NAND_FLASH_CMD, q_op.cmd_reg);  in qcom_param_page_type_exec()
2877 	nandc_set_reg(chip, NAND_ADDR0, 0);  in qcom_param_page_type_exec()
2878 	nandc_set_reg(chip, NAND_ADDR1, 0);  in qcom_param_page_type_exec()
2879 	nandc_set_reg(chip, NAND_DEV0_CFG0, 0 << CW_PER_PAGE  in qcom_param_page_type_exec()
2883 	nandc_set_reg(chip, NAND_DEV0_CFG1, 7 << NAND_RECOVERY_CYCLES  in qcom_param_page_type_exec()
2891 		nandc_set_reg(chip, NAND_EBI2_ECC_BUF_CFG, 1 << ECC_CFG_ECC_DISABLE);  in qcom_param_page_type_exec()
2895 		nandc_set_reg(chip, NAND_DEV_CMD_VLD,  in qcom_param_page_type_exec()
2897 		nandc_set_reg(chip, NAND_DEV_CMD1,  in qcom_param_page_type_exec()
2902 	nandc_set_reg(chip, NAND_EXEC_CMD, 1);  in qcom_param_page_type_exec()
2905 		nandc_set_reg(chip, NAND_DEV_CMD1_RESTORE, nandc->cmd1);  in qcom_param_page_type_exec()
2906 		nandc_set_reg(chip, NAND_DEV_CMD_VLD_RESTORE, nandc->vld);  in qcom_param_page_type_exec()