Lines Matching +full:0 +full:x00000064
11 #define HW_GPMI_CTRL0 0x00000000
12 #define HW_GPMI_CTRL0_SET 0x00000004
13 #define HW_GPMI_CTRL0_CLR 0x00000008
14 #define HW_GPMI_CTRL0_TOG 0x0000000c
20 #define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0
21 #define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1
22 #define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2
23 #define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3
26 #define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT 0x0
27 #define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT 0x1
36 #define LOCK_CS_ENABLE 0x1
37 #define BF_GPMI_CTRL0_LOCK_CS(v, x) 0x0
52 #define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x0
53 #define BV_GPMI_CTRL0_ADDRESS__NAND_CLE 0x1
54 #define BV_GPMI_CTRL0_ADDRESS__NAND_ALE 0x2
57 #define BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED 0x0
58 #define BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED 0x1
60 #define BP_GPMI_CTRL0_XFER_COUNT 0
61 #define BM_GPMI_CTRL0_XFER_COUNT (0xffff << BP_GPMI_CTRL0_XFER_COUNT)
65 #define HW_GPMI_COMPARE 0x00000010
67 #define HW_GPMI_ECCCTRL 0x00000020
68 #define HW_GPMI_ECCCTRL_SET 0x00000024
69 #define HW_GPMI_ECCCTRL_CLR 0x00000028
70 #define HW_GPMI_ECCCTRL_TOG 0x0000002c
76 #define BV_GPMI_ECCCTRL_ECC_CMD__BCH_DECODE 0x0
77 #define BV_GPMI_ECCCTRL_ECC_CMD__BCH_ENCODE 0x1
80 #define BV_GPMI_ECCCTRL_ENABLE_ECC__ENABLE 0x1
81 #define BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE 0x0
83 #define BP_GPMI_ECCCTRL_BUFFER_MASK 0
84 #define BM_GPMI_ECCCTRL_BUFFER_MASK (0x1ff << BP_GPMI_ECCCTRL_BUFFER_MASK)
87 #define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY 0x100
88 #define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE 0x1FF
90 #define HW_GPMI_ECCCOUNT 0x00000030
91 #define HW_GPMI_PAYLOAD 0x00000040
92 #define HW_GPMI_AUXILIARY 0x00000050
93 #define HW_GPMI_CTRL1 0x00000060
94 #define HW_GPMI_CTRL1_SET 0x00000064
95 #define HW_GPMI_CTRL1_CLR 0x00000068
96 #define HW_GPMI_CTRL1_TOG 0x0000006c
102 #define BM_GPMI_CTRL1_WRN_DLY_SEL (0x3 << BP_GPMI_CTRL1_WRN_DLY_SEL)
105 #define BV_GPMI_CTRL1_WRN_DLY_SEL_4_TO_8NS 0x0
106 #define BV_GPMI_CTRL1_WRN_DLY_SEL_6_TO_10NS 0x1
107 #define BV_GPMI_CTRL1_WRN_DLY_SEL_7_TO_12NS 0x2
108 #define BV_GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY 0x3
120 #define BM_GPMI_CTRL1_RDN_DELAY (0xf << BP_GPMI_CTRL1_RDN_DELAY)
125 #define BV_GPMI_CTRL1_DEV_RESET__ENABLED 0x0
126 #define BV_GPMI_CTRL1_DEV_RESET__DISABLED 0x1
129 #define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW 0x0
130 #define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH 0x1
133 #define BV_GPMI_CTRL1_GPMI_MODE__NAND 0x0
134 #define BV_GPMI_CTRL1_GPMI_MODE__ATA 0x1
136 #define BM_GPMI_CTRL1_GPMI_MODE (1 << 0)
143 #define HW_GPMI_TIMING0 0x00000070
146 #define BM_GPMI_TIMING0_ADDRESS_SETUP (0xff << BP_GPMI_TIMING0_ADDRESS_SETUP)
151 #define BM_GPMI_TIMING0_DATA_HOLD (0xff << BP_GPMI_TIMING0_DATA_HOLD)
155 #define BP_GPMI_TIMING0_DATA_SETUP 0
156 #define BM_GPMI_TIMING0_DATA_SETUP (0xff << BP_GPMI_TIMING0_DATA_SETUP)
160 #define HW_GPMI_TIMING1 0x00000080
162 #define BM_GPMI_TIMING1_BUSY_TIMEOUT (0xffff << BP_GPMI_TIMING1_BUSY_TIMEOUT)
166 #define HW_GPMI_TIMING2 0x00000090
167 #define HW_GPMI_DATA 0x000000a0
170 #define HW_GPMI_STAT 0x000000b0
172 #define MX28_BM_GPMI_STAT_READY_BUSY (0xff << MX28_BP_GPMI_STAT_READY_BUSY)
177 #define HW_GPMI_DEBUG 0x000000c0