Lines Matching +full:nand +full:- +full:ecc +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0
5 * Driver for NAND portions
11 * Based on drivers/mtd/nand/nomadik_nand.c (removed in v3.8)
20 #include <linux/dma-direction.h>
21 #include <linux/dma-mapping.h>
29 #include <linux/mtd/nand-ecc-sw-hamming.h>
37 #include <mtd/mtd-abi.h>
61 /* fsmc controller registers for NAND flash */
99 * TOUDEL = 7ns (Output delay from the flip-flops to the board)
120 * struct fsmc_nand_data - structure for FSMC NAND device state
124 * @nand: Chip related info for a NAND flash.
128 * @mode: Access mode
132 * @write_dma_chan: DMA channel for write access to NAND
135 * @dev_timings: NAND timings
137 * @data_pa: NAND Physical port for Data.
138 * @data_va: NAND port for Data.
139 * @cmd_va: NAND port for Command.
140 * @addr_va: NAND port for Address.
146 struct nand_chip nand; member
150 enum access_mode mode; member
172 if (section >= chip->ecc.steps) in fsmc_ecc1_ooblayout_ecc()
173 return -ERANGE; in fsmc_ecc1_ooblayout_ecc()
175 oobregion->offset = (section * 16) + 2; in fsmc_ecc1_ooblayout_ecc()
176 oobregion->length = 3; in fsmc_ecc1_ooblayout_ecc()
186 if (section >= chip->ecc.steps) in fsmc_ecc1_ooblayout_free()
187 return -ERANGE; in fsmc_ecc1_ooblayout_free()
189 oobregion->offset = (section * 16) + 8; in fsmc_ecc1_ooblayout_free()
191 if (section < chip->ecc.steps - 1) in fsmc_ecc1_ooblayout_free()
192 oobregion->length = 8; in fsmc_ecc1_ooblayout_free()
194 oobregion->length = mtd->oobsize - oobregion->offset; in fsmc_ecc1_ooblayout_free()
200 .ecc = fsmc_ecc1_ooblayout_ecc,
205 * ECC placement definitions in oobfree type format.
206 * There are 13 bytes of ecc for every 512 byte block and it has to be read
215 if (section >= chip->ecc.steps) in fsmc_ecc4_ooblayout_ecc()
216 return -ERANGE; in fsmc_ecc4_ooblayout_ecc()
218 oobregion->length = chip->ecc.bytes; in fsmc_ecc4_ooblayout_ecc()
220 if (!section && mtd->writesize <= 512) in fsmc_ecc4_ooblayout_ecc()
221 oobregion->offset = 0; in fsmc_ecc4_ooblayout_ecc()
223 oobregion->offset = (section * 16) + 2; in fsmc_ecc4_ooblayout_ecc()
233 if (section >= chip->ecc.steps) in fsmc_ecc4_ooblayout_free()
234 return -ERANGE; in fsmc_ecc4_ooblayout_free()
236 oobregion->offset = (section * 16) + 15; in fsmc_ecc4_ooblayout_free()
238 if (section < chip->ecc.steps - 1) in fsmc_ecc4_ooblayout_free()
239 oobregion->length = 3; in fsmc_ecc4_ooblayout_free()
241 oobregion->length = mtd->oobsize - oobregion->offset; in fsmc_ecc4_ooblayout_free()
247 .ecc = fsmc_ecc4_ooblayout_ecc,
253 return container_of(chip, struct fsmc_nand_data, nand); in nand_to_fsmc()
257 * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine
259 * This routine initializes timing parameters related to NAND memory access in
268 tclr = (tims->tclr & FSMC_TCLR_MASK) << FSMC_TCLR_SHIFT; in fsmc_nand_setup()
269 tar = (tims->tar & FSMC_TAR_MASK) << FSMC_TAR_SHIFT; in fsmc_nand_setup()
270 thiz = (tims->thiz & FSMC_THIZ_MASK) << FSMC_THIZ_SHIFT; in fsmc_nand_setup()
271 thold = (tims->thold & FSMC_THOLD_MASK) << FSMC_THOLD_SHIFT; in fsmc_nand_setup()
272 twait = (tims->twait & FSMC_TWAIT_MASK) << FSMC_TWAIT_SHIFT; in fsmc_nand_setup()
273 tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT; in fsmc_nand_setup()
275 if (host->nand.options & NAND_BUSWIDTH_16) in fsmc_nand_setup()
278 writel_relaxed(value | tclr | tar, host->regs_va + FSMC_PC); in fsmc_nand_setup()
279 writel_relaxed(thiz | thold | twait | tset, host->regs_va + COMM); in fsmc_nand_setup()
280 writel_relaxed(thiz | thold | twait | tset, host->regs_va + ATTRIB); in fsmc_nand_setup()
287 unsigned long hclk = clk_get_rate(host->clk); in fsmc_calc_timings()
291 if (sdrt->tRC_min < 30000) in fsmc_calc_timings()
292 return -EOPNOTSUPP; in fsmc_calc_timings()
294 tims->tar = DIV_ROUND_UP(sdrt->tAR_min / 1000, hclkn) - 1; in fsmc_calc_timings()
295 if (tims->tar > FSMC_TAR_MASK) in fsmc_calc_timings()
296 tims->tar = FSMC_TAR_MASK; in fsmc_calc_timings()
297 tims->tclr = DIV_ROUND_UP(sdrt->tCLR_min / 1000, hclkn) - 1; in fsmc_calc_timings()
298 if (tims->tclr > FSMC_TCLR_MASK) in fsmc_calc_timings()
299 tims->tclr = FSMC_TCLR_MASK; in fsmc_calc_timings()
301 thiz = sdrt->tCS_min - sdrt->tWP_min; in fsmc_calc_timings()
302 tims->thiz = DIV_ROUND_UP(thiz / 1000, hclkn); in fsmc_calc_timings()
304 thold = sdrt->tDH_min; in fsmc_calc_timings()
305 if (thold < sdrt->tCH_min) in fsmc_calc_timings()
306 thold = sdrt->tCH_min; in fsmc_calc_timings()
307 if (thold < sdrt->tCLH_min) in fsmc_calc_timings()
308 thold = sdrt->tCLH_min; in fsmc_calc_timings()
309 if (thold < sdrt->tWH_min) in fsmc_calc_timings()
310 thold = sdrt->tWH_min; in fsmc_calc_timings()
311 if (thold < sdrt->tALH_min) in fsmc_calc_timings()
312 thold = sdrt->tALH_min; in fsmc_calc_timings()
313 if (thold < sdrt->tREH_min) in fsmc_calc_timings()
314 thold = sdrt->tREH_min; in fsmc_calc_timings()
315 tims->thold = DIV_ROUND_UP(thold / 1000, hclkn); in fsmc_calc_timings()
316 if (tims->thold == 0) in fsmc_calc_timings()
317 tims->thold = 1; in fsmc_calc_timings()
318 else if (tims->thold > FSMC_THOLD_MASK) in fsmc_calc_timings()
319 tims->thold = FSMC_THOLD_MASK; in fsmc_calc_timings()
321 tset = max(sdrt->tCS_min - sdrt->tWP_min, in fsmc_calc_timings()
322 sdrt->tCEA_max - sdrt->tREA_max); in fsmc_calc_timings()
323 tims->tset = DIV_ROUND_UP(tset / 1000, hclkn) - 1; in fsmc_calc_timings()
324 if (tims->tset == 0) in fsmc_calc_timings()
325 tims->tset = 1; in fsmc_calc_timings()
326 else if (tims->tset > FSMC_TSET_MASK) in fsmc_calc_timings()
327 tims->tset = FSMC_TSET_MASK; in fsmc_calc_timings()
332 * twait >= tCEA - (tset * TCLK) + TOUTDEL + TINDEL in fsmc_calc_timings()
334 twait_min = sdrt->tCEA_max - ((tims->tset + 1) * hclkn * 1000) in fsmc_calc_timings()
336 twait = max3(sdrt->tRP_min, sdrt->tWP_min, twait_min); in fsmc_calc_timings()
338 tims->twait = DIV_ROUND_UP(twait / 1000, hclkn) - 1; in fsmc_calc_timings()
339 if (tims->twait == 0) in fsmc_calc_timings()
340 tims->twait = 1; in fsmc_calc_timings()
341 else if (tims->twait > FSMC_TWAIT_MASK) in fsmc_calc_timings()
342 tims->twait = FSMC_TWAIT_MASK; in fsmc_calc_timings()
347 static int fsmc_setup_interface(struct nand_chip *nand, int csline, in fsmc_setup_interface() argument
350 struct fsmc_nand_data *host = nand_to_fsmc(nand); in fsmc_setup_interface()
372 * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers
374 static void fsmc_enable_hwecc(struct nand_chip *chip, int mode) in fsmc_enable_hwecc() argument
378 writel_relaxed(readl(host->regs_va + FSMC_PC) & ~FSMC_ECCPLEN_256, in fsmc_enable_hwecc()
379 host->regs_va + FSMC_PC); in fsmc_enable_hwecc()
380 writel_relaxed(readl(host->regs_va + FSMC_PC) & ~FSMC_ECCEN, in fsmc_enable_hwecc()
381 host->regs_va + FSMC_PC); in fsmc_enable_hwecc()
382 writel_relaxed(readl(host->regs_va + FSMC_PC) | FSMC_ECCEN, in fsmc_enable_hwecc()
383 host->regs_va + FSMC_PC); in fsmc_enable_hwecc()
387 * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by
388 * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to
389 * max of 8-bits)
392 u8 *ecc) in fsmc_read_hwecc_ecc4() argument
399 if (readl_relaxed(host->regs_va + STS) & FSMC_CODE_RDY) in fsmc_read_hwecc_ecc4()
406 dev_err(host->dev, "calculate ecc timed out\n"); in fsmc_read_hwecc_ecc4()
407 return -ETIMEDOUT; in fsmc_read_hwecc_ecc4()
410 ecc_tmp = readl_relaxed(host->regs_va + ECC1); in fsmc_read_hwecc_ecc4()
411 ecc[0] = ecc_tmp; in fsmc_read_hwecc_ecc4()
412 ecc[1] = ecc_tmp >> 8; in fsmc_read_hwecc_ecc4()
413 ecc[2] = ecc_tmp >> 16; in fsmc_read_hwecc_ecc4()
414 ecc[3] = ecc_tmp >> 24; in fsmc_read_hwecc_ecc4()
416 ecc_tmp = readl_relaxed(host->regs_va + ECC2); in fsmc_read_hwecc_ecc4()
417 ecc[4] = ecc_tmp; in fsmc_read_hwecc_ecc4()
418 ecc[5] = ecc_tmp >> 8; in fsmc_read_hwecc_ecc4()
419 ecc[6] = ecc_tmp >> 16; in fsmc_read_hwecc_ecc4()
420 ecc[7] = ecc_tmp >> 24; in fsmc_read_hwecc_ecc4()
422 ecc_tmp = readl_relaxed(host->regs_va + ECC3); in fsmc_read_hwecc_ecc4()
423 ecc[8] = ecc_tmp; in fsmc_read_hwecc_ecc4()
424 ecc[9] = ecc_tmp >> 8; in fsmc_read_hwecc_ecc4()
425 ecc[10] = ecc_tmp >> 16; in fsmc_read_hwecc_ecc4()
426 ecc[11] = ecc_tmp >> 24; in fsmc_read_hwecc_ecc4()
428 ecc_tmp = readl_relaxed(host->regs_va + STS); in fsmc_read_hwecc_ecc4()
429 ecc[12] = ecc_tmp >> 16; in fsmc_read_hwecc_ecc4()
435 * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by
436 * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to
437 * max of 1-bit)
440 u8 *ecc) in fsmc_read_hwecc_ecc1() argument
445 ecc_tmp = readl_relaxed(host->regs_va + ECC1); in fsmc_read_hwecc_ecc1()
446 ecc[0] = ecc_tmp; in fsmc_read_hwecc_ecc1()
447 ecc[1] = ecc_tmp >> 8; in fsmc_read_hwecc_ecc1()
448 ecc[2] = ecc_tmp >> 16; in fsmc_read_hwecc_ecc1()
458 bool sm_order = chip->ecc.options & NAND_ECC_SOFT_HAMMING_SM_ORDER; in fsmc_correct_ecc1()
461 chip->ecc.size, sm_order); in fsmc_correct_ecc1()
482 complete(&host->dma_access_complete); in dma_complete()
498 chan = host->write_dma_chan; in dma_xfer()
500 chan = host->read_dma_chan; in dma_xfer()
502 return -EINVAL; in dma_xfer()
504 dma_dev = chan->device; in dma_xfer()
505 dma_addr = dma_map_single(dma_dev->dev, buffer, len, direction); in dma_xfer()
509 dma_dst = host->data_pa; in dma_xfer()
511 dma_src = host->data_pa; in dma_xfer()
515 tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src, in dma_xfer()
518 dev_err(host->dev, "device_prep_dma_memcpy error\n"); in dma_xfer()
519 ret = -EIO; in dma_xfer()
523 tx->callback = dma_complete; in dma_xfer()
524 tx->callback_param = host; in dma_xfer()
525 cookie = tx->tx_submit(tx); in dma_xfer()
529 dev_err(host->dev, "dma_submit_error %d\n", cookie); in dma_xfer()
536 wait_for_completion_timeout(&host->dma_access_complete, in dma_xfer()
540 dev_err(host->dev, "wait_for_completion_timeout\n"); in dma_xfer()
541 ret = -ETIMEDOUT; in dma_xfer()
548 dma_unmap_single(dma_dev->dev, dma_addr, len, direction); in dma_xfer()
554 * fsmc_write_buf - write buffer to chip
555 * @host: FSMC NAND controller
570 writel_relaxed(p[i], host->data_va); in fsmc_write_buf()
573 writeb_relaxed(buf[i], host->data_va); in fsmc_write_buf()
578 * fsmc_read_buf - read chip data into buffer
579 * @host: FSMC NAND controller
593 p[i] = readl_relaxed(host->data_va); in fsmc_read_buf()
596 buf[i] = readb_relaxed(host->data_va); in fsmc_read_buf()
601 * fsmc_read_buf_dma - read chip data into buffer
602 * @host: FSMC NAND controller
613 * fsmc_write_buf_dma - write buffer to chip
614 * @host: FSMC NAND controller
625 * fsmc_exec_op - hook called by the core to execute NAND operations
642 pr_debug("Executing operation [%d instructions]:\n", op->ninstrs); in fsmc_exec_op()
644 for (op_id = 0; op_id < op->ninstrs; op_id++) { in fsmc_exec_op()
645 instr = &op->instrs[op_id]; in fsmc_exec_op()
649 switch (instr->type) { in fsmc_exec_op()
651 writeb_relaxed(instr->ctx.cmd.opcode, host->cmd_va); in fsmc_exec_op()
655 for (i = 0; i < instr->ctx.addr.naddrs; i++) in fsmc_exec_op()
656 writeb_relaxed(instr->ctx.addr.addrs[i], in fsmc_exec_op()
657 host->addr_va); in fsmc_exec_op()
661 if (host->mode == USE_DMA_ACCESS) in fsmc_exec_op()
662 fsmc_read_buf_dma(host, instr->ctx.data.buf.in, in fsmc_exec_op()
663 instr->ctx.data.len); in fsmc_exec_op()
665 fsmc_read_buf(host, instr->ctx.data.buf.in, in fsmc_exec_op()
666 instr->ctx.data.len); in fsmc_exec_op()
670 if (host->mode == USE_DMA_ACCESS) in fsmc_exec_op()
672 instr->ctx.data.buf.out, in fsmc_exec_op()
673 instr->ctx.data.len); in fsmc_exec_op()
675 fsmc_write_buf(host, instr->ctx.data.buf.out, in fsmc_exec_op()
676 instr->ctx.data.len); in fsmc_exec_op()
681 instr->ctx.waitrdy.timeout_ms); in fsmc_exec_op()
685 if (instr->delay_ns) in fsmc_exec_op()
686 ndelay(instr->delay_ns); in fsmc_exec_op()
694 * @chip: nand chip info structure
696 * @oob_required: caller expects OOB data read to chip->oob_poi
699 * This routine is needed for fsmc version 8 as reading from NAND chip has to be
701 * data(512 byte) -> ecc(13 byte)
709 int i, j, s, stat, eccsize = chip->ecc.size; in fsmc_read_page_hwecc()
710 int eccbytes = chip->ecc.bytes; in fsmc_read_page_hwecc()
711 int eccsteps = chip->ecc.steps; in fsmc_read_page_hwecc()
713 u8 *ecc_calc = chip->ecc.calc_buf; in fsmc_read_page_hwecc()
714 u8 *ecc_code = chip->ecc.code_buf; in fsmc_read_page_hwecc()
727 chip->ecc.hwctl(chip, NAND_ECC_READ); in fsmc_read_page_hwecc()
744 * to read at least 13 bytes even in case of 16 bit NAND in fsmc_read_page_hwecc()
747 if (chip->options & NAND_BUSWIDTH_16) in fsmc_read_page_hwecc()
754 memcpy(&ecc_code[i], oob, chip->ecc.bytes); in fsmc_read_page_hwecc()
755 chip->ecc.calculate(chip, p, &ecc_calc[i]); in fsmc_read_page_hwecc()
757 stat = chip->ecc.correct(chip, p, &ecc_code[i], &ecc_calc[i]); in fsmc_read_page_hwecc()
759 mtd->ecc_stats.failed++; in fsmc_read_page_hwecc()
761 mtd->ecc_stats.corrected += stat; in fsmc_read_page_hwecc()
773 * @read_ecc: ecc read from device spare area
774 * @calc_ecc: ecc calculated from read data
787 num_err = (readl_relaxed(host->regs_va + STS) >> 10) & 0xF; in fsmc_bch8_correct_data()
797 * would result in an ecc error because the oob data is also in fsmc_bch8_correct_data()
798 * erased to FF and the calculated ecc for an FF data is not in fsmc_bch8_correct_data()
809 int bits_ecc = count_written_bits(read_ecc, chip->ecc.bytes, 8); in fsmc_bch8_correct_data()
810 int bits_data = count_written_bits(dat, chip->ecc.size, 8); in fsmc_bch8_correct_data()
814 memset(dat, 0xff, chip->ecc.size); in fsmc_bch8_correct_data()
818 return -EBADMSG; in fsmc_bch8_correct_data()
822 * ------------------- calc_ecc[] bit wise -----------|--13 bits--| in fsmc_bch8_correct_data()
823 * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--| in fsmc_bch8_correct_data()
830 ecc1 = readl_relaxed(host->regs_va + ECC1); in fsmc_bch8_correct_data()
831 ecc2 = readl_relaxed(host->regs_va + ECC2); in fsmc_bch8_correct_data()
832 ecc3 = readl_relaxed(host->regs_va + ECC3); in fsmc_bch8_correct_data()
833 ecc4 = readl_relaxed(host->regs_va + STS); in fsmc_bch8_correct_data()
845 while (num_err--) { in fsmc_bch8_correct_data()
848 if (err_idx[i] < chip->ecc.size * 8) { in fsmc_bch8_correct_data()
860 chan->private = slave; in filter()
866 struct nand_chip *nand) in fsmc_nand_probe_config_dt() argument
868 struct device_node *np = pdev->dev.of_node; in fsmc_nand_probe_config_dt()
872 nand->options = 0; in fsmc_nand_probe_config_dt()
874 if (!of_property_read_u32(np, "bank-width", &val)) { in fsmc_nand_probe_config_dt()
876 nand->options |= NAND_BUSWIDTH_16; in fsmc_nand_probe_config_dt()
878 dev_err(&pdev->dev, "invalid bank-width %u\n", val); in fsmc_nand_probe_config_dt()
879 return -EINVAL; in fsmc_nand_probe_config_dt()
883 if (of_property_read_bool(np, "nand-skip-bbtscan")) in fsmc_nand_probe_config_dt()
884 nand->options |= NAND_SKIP_BBTSCAN; in fsmc_nand_probe_config_dt()
886 host->dev_timings = devm_kzalloc(&pdev->dev, in fsmc_nand_probe_config_dt()
887 sizeof(*host->dev_timings), in fsmc_nand_probe_config_dt()
889 if (!host->dev_timings) in fsmc_nand_probe_config_dt()
890 return -ENOMEM; in fsmc_nand_probe_config_dt()
892 ret = of_property_read_u8_array(np, "timings", (u8 *)host->dev_timings, in fsmc_nand_probe_config_dt()
893 sizeof(*host->dev_timings)); in fsmc_nand_probe_config_dt()
895 host->dev_timings = NULL; in fsmc_nand_probe_config_dt()
897 /* Set default NAND bank to 0 */ in fsmc_nand_probe_config_dt()
898 host->bank = 0; in fsmc_nand_probe_config_dt()
901 dev_err(&pdev->dev, "invalid bank %u\n", val); in fsmc_nand_probe_config_dt()
902 return -EINVAL; in fsmc_nand_probe_config_dt()
904 host->bank = val; in fsmc_nand_probe_config_dt()
909 static int fsmc_nand_attach_chip(struct nand_chip *nand) in fsmc_nand_attach_chip() argument
911 struct mtd_info *mtd = nand_to_mtd(nand); in fsmc_nand_attach_chip()
912 struct fsmc_nand_data *host = nand_to_fsmc(nand); in fsmc_nand_attach_chip()
914 if (nand->ecc.engine_type == NAND_ECC_ENGINE_TYPE_INVALID) in fsmc_nand_attach_chip()
915 nand->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; in fsmc_nand_attach_chip()
917 if (!nand->ecc.size) in fsmc_nand_attach_chip()
918 nand->ecc.size = 512; in fsmc_nand_attach_chip()
920 if (AMBA_REV_BITS(host->pid) >= 8) { in fsmc_nand_attach_chip()
921 nand->ecc.read_page = fsmc_read_page_hwecc; in fsmc_nand_attach_chip()
922 nand->ecc.calculate = fsmc_read_hwecc_ecc4; in fsmc_nand_attach_chip()
923 nand->ecc.correct = fsmc_bch8_correct_data; in fsmc_nand_attach_chip()
924 nand->ecc.bytes = 13; in fsmc_nand_attach_chip()
925 nand->ecc.strength = 8; in fsmc_nand_attach_chip()
928 if (AMBA_REV_BITS(host->pid) >= 8) { in fsmc_nand_attach_chip()
929 switch (mtd->oobsize) { in fsmc_nand_attach_chip()
937 dev_warn(host->dev, in fsmc_nand_attach_chip()
939 mtd->oobsize); in fsmc_nand_attach_chip()
940 return -EINVAL; in fsmc_nand_attach_chip()
948 switch (nand->ecc.engine_type) { in fsmc_nand_attach_chip()
950 dev_info(host->dev, "Using 1-bit HW ECC scheme\n"); in fsmc_nand_attach_chip()
951 nand->ecc.calculate = fsmc_read_hwecc_ecc1; in fsmc_nand_attach_chip()
952 nand->ecc.correct = fsmc_correct_ecc1; in fsmc_nand_attach_chip()
953 nand->ecc.hwctl = fsmc_enable_hwecc; in fsmc_nand_attach_chip()
954 nand->ecc.bytes = 3; in fsmc_nand_attach_chip()
955 nand->ecc.strength = 1; in fsmc_nand_attach_chip()
956 nand->ecc.options |= NAND_ECC_SOFT_HAMMING_SM_ORDER; in fsmc_nand_attach_chip()
960 if (nand->ecc.algo == NAND_ECC_ALGO_BCH) { in fsmc_nand_attach_chip()
961 dev_info(host->dev, in fsmc_nand_attach_chip()
962 "Using 4-bit SW BCH ECC scheme\n"); in fsmc_nand_attach_chip()
971 dev_err(host->dev, "Unsupported ECC mode!\n"); in fsmc_nand_attach_chip()
972 return -ENOTSUPP; in fsmc_nand_attach_chip()
976 * Don't set layout for BCH4 SW ECC. This will be in fsmc_nand_attach_chip()
979 if (nand->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) { in fsmc_nand_attach_chip()
980 switch (mtd->oobsize) { in fsmc_nand_attach_chip()
988 dev_warn(host->dev, in fsmc_nand_attach_chip()
990 mtd->oobsize); in fsmc_nand_attach_chip()
991 return -EINVAL; in fsmc_nand_attach_chip()
1005 * fsmc_nand_disable() - Disables the NAND bank
1012 val = readl(host->regs_va + FSMC_PC); in fsmc_nand_disable()
1014 writel(val, host->regs_va + FSMC_PC); in fsmc_nand_disable()
1018 * fsmc_nand_probe - Probe function
1025 struct nand_chip *nand; in fsmc_nand_probe() local
1034 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL); in fsmc_nand_probe()
1036 return -ENOMEM; in fsmc_nand_probe()
1038 nand = &host->nand; in fsmc_nand_probe()
1040 ret = fsmc_nand_probe_config_dt(pdev, host, nand); in fsmc_nand_probe()
1045 host->data_va = devm_ioremap_resource(&pdev->dev, res); in fsmc_nand_probe()
1046 if (IS_ERR(host->data_va)) in fsmc_nand_probe()
1047 return PTR_ERR(host->data_va); in fsmc_nand_probe()
1049 host->data_pa = (dma_addr_t)res->start; in fsmc_nand_probe()
1052 host->addr_va = devm_ioremap_resource(&pdev->dev, res); in fsmc_nand_probe()
1053 if (IS_ERR(host->addr_va)) in fsmc_nand_probe()
1054 return PTR_ERR(host->addr_va); in fsmc_nand_probe()
1057 host->cmd_va = devm_ioremap_resource(&pdev->dev, res); in fsmc_nand_probe()
1058 if (IS_ERR(host->cmd_va)) in fsmc_nand_probe()
1059 return PTR_ERR(host->cmd_va); in fsmc_nand_probe()
1062 base = devm_ioremap_resource(&pdev->dev, res); in fsmc_nand_probe()
1066 host->regs_va = base + FSMC_NOR_REG_SIZE + in fsmc_nand_probe()
1067 (host->bank * FSMC_NAND_BANK_SZ); in fsmc_nand_probe()
1069 host->clk = devm_clk_get_enabled(&pdev->dev, NULL); in fsmc_nand_probe()
1070 if (IS_ERR(host->clk)) { in fsmc_nand_probe()
1071 dev_err(&pdev->dev, "failed to fetch block clock\n"); in fsmc_nand_probe()
1072 return PTR_ERR(host->clk); in fsmc_nand_probe()
1080 pid |= (readl(base + resource_size(res) - 0x20 + 4 * i) & in fsmc_nand_probe()
1083 host->pid = pid; in fsmc_nand_probe()
1085 dev_info(&pdev->dev, in fsmc_nand_probe()
1090 host->dev = &pdev->dev; in fsmc_nand_probe()
1092 if (host->mode == USE_DMA_ACCESS) in fsmc_nand_probe()
1093 init_completion(&host->dma_access_complete); in fsmc_nand_probe()
1096 mtd = nand_to_mtd(&host->nand); in fsmc_nand_probe()
1097 nand_set_flash_node(nand, pdev->dev.of_node); in fsmc_nand_probe()
1099 mtd->dev.parent = &pdev->dev; in fsmc_nand_probe()
1101 nand->badblockbits = 7; in fsmc_nand_probe()
1103 if (host->mode == USE_DMA_ACCESS) { in fsmc_nand_probe()
1106 host->read_dma_chan = dma_request_channel(mask, filter, NULL); in fsmc_nand_probe()
1107 if (!host->read_dma_chan) { in fsmc_nand_probe()
1108 dev_err(&pdev->dev, "Unable to get read dma channel\n"); in fsmc_nand_probe()
1109 ret = -ENODEV; in fsmc_nand_probe()
1112 host->write_dma_chan = dma_request_channel(mask, filter, NULL); in fsmc_nand_probe()
1113 if (!host->write_dma_chan) { in fsmc_nand_probe()
1114 dev_err(&pdev->dev, "Unable to get write dma channel\n"); in fsmc_nand_probe()
1115 ret = -ENODEV; in fsmc_nand_probe()
1120 if (host->dev_timings) { in fsmc_nand_probe()
1121 fsmc_nand_setup(host, host->dev_timings); in fsmc_nand_probe()
1122 nand->options |= NAND_KEEP_TIMINGS; in fsmc_nand_probe()
1125 nand_controller_init(&host->base); in fsmc_nand_probe()
1126 host->base.ops = &fsmc_nand_controller_ops; in fsmc_nand_probe()
1127 nand->controller = &host->base; in fsmc_nand_probe()
1132 ret = nand_scan(nand, 1); in fsmc_nand_probe()
1136 mtd->name = "nand"; in fsmc_nand_probe()
1142 dev_info(&pdev->dev, "FSMC NAND driver registration successful\n"); in fsmc_nand_probe()
1147 nand_cleanup(nand); in fsmc_nand_probe()
1149 if (host->mode == USE_DMA_ACCESS) in fsmc_nand_probe()
1150 dma_release_channel(host->write_dma_chan); in fsmc_nand_probe()
1152 if (host->mode == USE_DMA_ACCESS) in fsmc_nand_probe()
1153 dma_release_channel(host->read_dma_chan); in fsmc_nand_probe()
1168 struct nand_chip *chip = &host->nand; in fsmc_nand_remove()
1176 if (host->mode == USE_DMA_ACCESS) { in fsmc_nand_remove()
1177 dma_release_channel(host->write_dma_chan); in fsmc_nand_remove()
1178 dma_release_channel(host->read_dma_chan); in fsmc_nand_remove()
1189 clk_disable_unprepare(host->clk); in fsmc_nand_suspend()
1200 ret = clk_prepare_enable(host->clk); in fsmc_nand_resume()
1205 if (host->dev_timings) in fsmc_nand_resume()
1206 fsmc_nand_setup(host, host->dev_timings); in fsmc_nand_resume()
1207 nand_reset(&host->nand, 0); in fsmc_nand_resume()
1217 { .compatible = "st,spear600-fsmc-nand" },
1218 { .compatible = "stericsson,fsmc-nand" },
1226 .name = "fsmc-nand",
1236 MODULE_DESCRIPTION("NAND driver for SPEAr Platforms");