Lines Matching +full:bank +full:- +full:number
1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright (c) 2009 - 2010, Intel Corporation and its suppliers.
18 #define DEVICE_RESET__BANK(bank) BIT(bank) argument
36 #define RB_PIN_ENABLED__BANK(bank) BIT(bank) argument
208 #define INTR_STATUS(bank) (0x410 + (bank) * 0x50) argument
209 #define INTR_EN(bank) (0x420 + (bank) * 0x50) argument
230 #define PAGE_CNT(bank) (0x430 + (bank) * 0x50) argument
231 #define ERR_PAGE_ADDR(bank) (0x440 + (bank) * 0x50) argument
232 #define ERR_BLOCK_ADDR(bank) (0x450 + (bank) * 0x50) argument
254 #define ECC_COR_INFO(bank) (0x650 + (bank) / 2 * 0x10) argument
255 #define ECC_COR_INFO__SHIFT(bank) ((bank) % 2 * 8) argument
295 * struct denali_chip_sel - per-CS data of Denali NAND
297 * @bank: bank id of the controller this CS is connected to
308 int bank; member
320 * struct denali_chip - per-chip data of Denali NAND
324 * @nsels: the number of CS lines of this chip
325 * @sels: the array of per-cs data
335 * struct denali_controller - Denali NAND controller data
345 * @irq: interrupt number
350 * @devs_per_cs: number of devices connected in parallel
351 * @oob_skip_bytes: number of bytes in OOB skipped by the ECC engine
352 * @active_bank: active bank id
353 * @nbanks: the number of banks supported by this controller
355 * @caps: controller capabilities that cannot be detected run-time