Lines Matching +full:0 +full:x650
17 #define DEVICE_RESET 0x0
20 #define TRANSFER_SPARE_REG 0x10
21 #define TRANSFER_SPARE_REG__FLAG BIT(0)
23 #define LOAD_WAIT_CNT 0x20
24 #define LOAD_WAIT_CNT__VALUE GENMASK(15, 0)
26 #define PROGRAM_WAIT_CNT 0x30
27 #define PROGRAM_WAIT_CNT__VALUE GENMASK(15, 0)
29 #define ERASE_WAIT_CNT 0x40
30 #define ERASE_WAIT_CNT__VALUE GENMASK(15, 0)
32 #define INT_MON_CYCCNT 0x50
33 #define INT_MON_CYCCNT__VALUE GENMASK(15, 0)
35 #define RB_PIN_ENABLED 0x60
38 #define MULTIPLANE_OPERATION 0x70
39 #define MULTIPLANE_OPERATION__FLAG BIT(0)
41 #define MULTIPLANE_READ_ENABLE 0x80
42 #define MULTIPLANE_READ_ENABLE__FLAG BIT(0)
44 #define COPYBACK_DISABLE 0x90
45 #define COPYBACK_DISABLE__FLAG BIT(0)
47 #define CACHE_WRITE_ENABLE 0xa0
48 #define CACHE_WRITE_ENABLE__FLAG BIT(0)
50 #define CACHE_READ_ENABLE 0xb0
51 #define CACHE_READ_ENABLE__FLAG BIT(0)
53 #define PREFETCH_MODE 0xc0
54 #define PREFETCH_MODE__PREFETCH_EN BIT(0)
57 #define CHIP_ENABLE_DONT_CARE 0xd0
58 #define CHIP_EN_DONT_CARE__FLAG BIT(0)
60 #define ECC_ENABLE 0xe0
61 #define ECC_ENABLE__FLAG BIT(0)
63 #define GLOBAL_INT_ENABLE 0xf0
64 #define GLOBAL_INT_EN_FLAG BIT(0)
66 #define TWHR2_AND_WE_2_RE 0x100
67 #define TWHR2_AND_WE_2_RE__WE_2_RE GENMASK(5, 0)
70 #define TCWAW_AND_ADDR_2_DATA 0x110
72 #define TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA GENMASK(6, 0)
75 #define RE_2_WE 0x120
76 #define RE_2_WE__VALUE GENMASK(5, 0)
78 #define ACC_CLKS 0x130
79 #define ACC_CLKS__VALUE GENMASK(3, 0)
81 #define NUMBER_OF_PLANES 0x140
82 #define NUMBER_OF_PLANES__VALUE GENMASK(2, 0)
84 #define PAGES_PER_BLOCK 0x150
85 #define PAGES_PER_BLOCK__VALUE GENMASK(15, 0)
87 #define DEVICE_WIDTH 0x160
88 #define DEVICE_WIDTH__VALUE GENMASK(1, 0)
90 #define DEVICE_MAIN_AREA_SIZE 0x170
91 #define DEVICE_MAIN_AREA_SIZE__VALUE GENMASK(15, 0)
93 #define DEVICE_SPARE_AREA_SIZE 0x180
94 #define DEVICE_SPARE_AREA_SIZE__VALUE GENMASK(15, 0)
96 #define TWO_ROW_ADDR_CYCLES 0x190
97 #define TWO_ROW_ADDR_CYCLES__FLAG BIT(0)
99 #define MULTIPLANE_ADDR_RESTRICT 0x1a0
100 #define MULTIPLANE_ADDR_RESTRICT__FLAG BIT(0)
102 #define ECC_CORRECTION 0x1b0
103 #define ECC_CORRECTION__VALUE GENMASK(4, 0)
106 #define READ_MODE 0x1c0
107 #define READ_MODE__VALUE GENMASK(3, 0)
109 #define WRITE_MODE 0x1d0
110 #define WRITE_MODE__VALUE GENMASK(3, 0)
112 #define COPYBACK_MODE 0x1e0
113 #define COPYBACK_MODE__VALUE GENMASK(3, 0)
115 #define RDWR_EN_LO_CNT 0x1f0
116 #define RDWR_EN_LO_CNT__VALUE GENMASK(4, 0)
118 #define RDWR_EN_HI_CNT 0x200
119 #define RDWR_EN_HI_CNT__VALUE GENMASK(4, 0)
121 #define MAX_RD_DELAY 0x210
122 #define MAX_RD_DELAY__VALUE GENMASK(3, 0)
124 #define CS_SETUP_CNT 0x220
125 #define CS_SETUP_CNT__VALUE GENMASK(4, 0)
128 #define SPARE_AREA_SKIP_BYTES 0x230
129 #define SPARE_AREA_SKIP_BYTES__VALUE GENMASK(5, 0)
131 #define SPARE_AREA_MARKER 0x240
132 #define SPARE_AREA_MARKER__VALUE GENMASK(15, 0)
134 #define DEVICES_CONNECTED 0x250
135 #define DEVICES_CONNECTED__VALUE GENMASK(2, 0)
137 #define DIE_MASK 0x260
138 #define DIE_MASK__VALUE GENMASK(7, 0)
140 #define FIRST_BLOCK_OF_NEXT_PLANE 0x270
141 #define FIRST_BLOCK_OF_NEXT_PLANE__VALUE GENMASK(15, 0)
143 #define WRITE_PROTECT 0x280
144 #define WRITE_PROTECT__FLAG BIT(0)
146 #define RE_2_RE 0x290
147 #define RE_2_RE__VALUE GENMASK(5, 0)
149 #define MANUFACTURER_ID 0x300
150 #define MANUFACTURER_ID__VALUE GENMASK(7, 0)
152 #define DEVICE_ID 0x310
153 #define DEVICE_ID__VALUE GENMASK(7, 0)
155 #define DEVICE_PARAM_0 0x320
156 #define DEVICE_PARAM_0__VALUE GENMASK(7, 0)
158 #define DEVICE_PARAM_1 0x330
159 #define DEVICE_PARAM_1__VALUE GENMASK(7, 0)
161 #define DEVICE_PARAM_2 0x340
162 #define DEVICE_PARAM_2__VALUE GENMASK(7, 0)
164 #define LOGICAL_PAGE_DATA_SIZE 0x350
165 #define LOGICAL_PAGE_DATA_SIZE__VALUE GENMASK(15, 0)
167 #define LOGICAL_PAGE_SPARE_SIZE 0x360
168 #define LOGICAL_PAGE_SPARE_SIZE__VALUE GENMASK(15, 0)
170 #define REVISION 0x370
171 #define REVISION__VALUE GENMASK(15, 0)
173 #define ONFI_DEVICE_FEATURES 0x380
174 #define ONFI_DEVICE_FEATURES__VALUE GENMASK(5, 0)
176 #define ONFI_OPTIONAL_COMMANDS 0x390
177 #define ONFI_OPTIONAL_COMMANDS__VALUE GENMASK(5, 0)
179 #define ONFI_TIMING_MODE 0x3a0
180 #define ONFI_TIMING_MODE__VALUE GENMASK(5, 0)
182 #define ONFI_PGM_CACHE_TIMING_MODE 0x3b0
183 #define ONFI_PGM_CACHE_TIMING_MODE__VALUE GENMASK(5, 0)
185 #define ONFI_DEVICE_NO_OF_LUNS 0x3c0
186 #define ONFI_DEVICE_NO_OF_LUNS__NO_OF_LUNS GENMASK(7, 0)
189 #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L 0x3d0
190 #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L__VALUE GENMASK(15, 0)
192 #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U 0x3e0
193 #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U__VALUE GENMASK(15, 0)
195 #define FEATURES 0x3f0
196 #define FEATURES__N_BANKS GENMASK(1, 0)
205 #define TRANSFER_MODE 0x400
206 #define TRANSFER_MODE__VALUE GENMASK(1, 0)
208 #define INTR_STATUS(bank) (0x410 + (bank) * 0x50)
209 #define INTR_EN(bank) (0x420 + (bank) * 0x50)
210 /* bit[1:0] is used differently depending on IP version */
211 #define INTR__ECC_UNCOR_ERR BIT(0) /* new IP */
212 #define INTR__ECC_TRANSACTION_DONE BIT(0) /* old IP */
230 #define PAGE_CNT(bank) (0x430 + (bank) * 0x50)
231 #define ERR_PAGE_ADDR(bank) (0x440 + (bank) * 0x50)
232 #define ERR_BLOCK_ADDR(bank) (0x450 + (bank) * 0x50)
234 #define ECC_THRESHOLD 0x600
235 #define ECC_THRESHOLD__VALUE GENMASK(9, 0)
237 #define ECC_ERROR_BLOCK_ADDRESS 0x610
238 #define ECC_ERROR_BLOCK_ADDRESS__VALUE GENMASK(15, 0)
240 #define ECC_ERROR_PAGE_ADDRESS 0x620
241 #define ECC_ERROR_PAGE_ADDRESS__VALUE GENMASK(11, 0)
244 #define ECC_ERROR_ADDRESS 0x630
245 #define ECC_ERROR_ADDRESS__OFFSET GENMASK(11, 0)
248 #define ERR_CORRECTION_INFO 0x640
249 #define ERR_CORRECTION_INFO__BYTE GENMASK(7, 0)
254 #define ECC_COR_INFO(bank) (0x650 + (bank) / 2 * 0x10)
256 #define ECC_COR_INFO__MAX_ERRORS GENMASK(6, 0)
259 #define CFG_DATA_BLOCK_SIZE 0x6b0
261 #define CFG_LAST_DATA_BLOCK_SIZE 0x6c0
263 #define CFG_NUM_DATA_BLOCKS 0x6d0
265 #define CFG_META_DATA_SIZE 0x6e0
267 #define DMA_ENABLE 0x700
268 #define DMA_ENABLE__FLAG BIT(0)
270 #define IGNORE_ECC_DONE 0x710
271 #define IGNORE_ECC_DONE__FLAG BIT(0)
273 #define DMA_INTR 0x720
274 #define DMA_INTR_EN 0x730
275 #define DMA_INTR__TARGET_ERROR BIT(0)
282 #define TARGET_ERR_ADDR_LO 0x740
283 #define TARGET_ERR_ADDR_LO__VALUE GENMASK(15, 0)
285 #define TARGET_ERR_ADDR_HI 0x750
286 #define TARGET_ERR_ADDR_HI__VALUE GENMASK(15, 0)
288 #define CHNL_ACTIVE 0x760
289 #define CHNL_ACTIVE__CHANNEL0 BIT(0)
389 #define DENALI_CAP_HW_ECC_FIXUP BIT(0)