Lines Matching +full:axi +full:- +full:max +full:- +full:burst +full:- +full:len
1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright © 2009-2010, Intel Corporation and its suppliers.
6 * Copyright (c) 2017-2019 Socionext Inc.
12 #include <linux/dma-mapping.h>
23 #define DENALI_NAND_NAME "denali-nand"
31 #define DENALI_MAP10 (2 << 26) /* high-level control plane */
39 #define DENALI_BANK(denali) ((denali)->active_bank << 24)
41 #define DENALI_INVALID_BANK -1
50 return container_of(chip->controller, struct denali_controller, in to_denali_controller()
55 * Direct Addressing - the slave address forms the control information (command
61 return ioread32(denali->host + addr); in denali_direct_read()
67 iowrite32(data, denali->host + addr); in denali_direct_write()
71 * Indexed Addressing - address translation module intervenes in passing the
78 iowrite32(addr, denali->host + DENALI_INDEXED_CTRL); in denali_indexed_read()
79 return ioread32(denali->host + DENALI_INDEXED_DATA); in denali_indexed_read()
85 iowrite32(addr, denali->host + DENALI_INDEXED_CTRL); in denali_indexed_write()
86 iowrite32(data, denali->host + DENALI_INDEXED_DATA); in denali_indexed_write()
93 for (i = 0; i < denali->nbanks; i++) in denali_enable_irq()
94 iowrite32(U32_MAX, denali->reg + INTR_EN(i)); in denali_enable_irq()
95 iowrite32(GLOBAL_INT_EN_FLAG, denali->reg + GLOBAL_INT_ENABLE); in denali_enable_irq()
102 for (i = 0; i < denali->nbanks; i++) in denali_disable_irq()
103 iowrite32(0, denali->reg + INTR_EN(i)); in denali_disable_irq()
104 iowrite32(0, denali->reg + GLOBAL_INT_ENABLE); in denali_disable_irq()
111 iowrite32(irq_status, denali->reg + INTR_STATUS(bank)); in denali_clear_irq()
118 for (i = 0; i < denali->nbanks; i++) in denali_clear_irq_all()
129 spin_lock(&denali->irq_lock); in denali_isr()
131 for (i = 0; i < denali->nbanks; i++) { in denali_isr()
132 irq_status = ioread32(denali->reg + INTR_STATUS(i)); in denali_isr()
138 if (i != denali->active_bank) in denali_isr()
141 denali->irq_status |= irq_status; in denali_isr()
143 if (denali->irq_status & denali->irq_mask) in denali_isr()
144 complete(&denali->complete); in denali_isr()
147 spin_unlock(&denali->irq_lock); in denali_isr()
156 spin_lock_irqsave(&denali->irq_lock, flags); in denali_reset_irq()
157 denali->irq_status = 0; in denali_reset_irq()
158 denali->irq_mask = 0; in denali_reset_irq()
159 spin_unlock_irqrestore(&denali->irq_lock, flags); in denali_reset_irq()
167 spin_lock_irqsave(&denali->irq_lock, flags); in denali_wait_for_irq()
169 irq_status = denali->irq_status; in denali_wait_for_irq()
173 spin_unlock_irqrestore(&denali->irq_lock, flags); in denali_wait_for_irq()
177 denali->irq_mask = irq_mask; in denali_wait_for_irq()
178 reinit_completion(&denali->complete); in denali_wait_for_irq()
179 spin_unlock_irqrestore(&denali->irq_lock, flags); in denali_wait_for_irq()
181 time_left = wait_for_completion_timeout(&denali->complete, in denali_wait_for_irq()
184 dev_err(denali->dev, "timeout while waiting for irq 0x%x\n", in denali_wait_for_irq()
189 return denali->irq_status; in denali_wait_for_irq()
195 struct denali_chip_sel *sel = &to_denali_chip(chip)->sels[cs]; in denali_select_target()
198 denali->active_bank = sel->bank; in denali_select_target()
200 iowrite32(1 << (chip->phys_erase_shift - chip->page_shift), in denali_select_target()
201 denali->reg + PAGES_PER_BLOCK); in denali_select_target()
202 iowrite32(chip->options & NAND_BUSWIDTH_16 ? 1 : 0, in denali_select_target()
203 denali->reg + DEVICE_WIDTH); in denali_select_target()
204 iowrite32(mtd->writesize, denali->reg + DEVICE_MAIN_AREA_SIZE); in denali_select_target()
205 iowrite32(mtd->oobsize, denali->reg + DEVICE_SPARE_AREA_SIZE); in denali_select_target()
206 iowrite32(chip->options & NAND_ROW_ADDR_3 ? in denali_select_target()
208 denali->reg + TWO_ROW_ADDR_CYCLES); in denali_select_target()
210 FIELD_PREP(ECC_CORRECTION__VALUE, chip->ecc.strength), in denali_select_target()
211 denali->reg + ECC_CORRECTION); in denali_select_target()
212 iowrite32(chip->ecc.size, denali->reg + CFG_DATA_BLOCK_SIZE); in denali_select_target()
213 iowrite32(chip->ecc.size, denali->reg + CFG_LAST_DATA_BLOCK_SIZE); in denali_select_target()
214 iowrite32(chip->ecc.steps, denali->reg + CFG_NUM_DATA_BLOCKS); in denali_select_target()
216 if (chip->options & NAND_KEEP_TIMINGS) in denali_select_target()
220 iowrite32(sel->hwhr2_and_we_2_re, denali->reg + TWHR2_AND_WE_2_RE); in denali_select_target()
221 iowrite32(sel->tcwaw_and_addr_2_data, in denali_select_target()
222 denali->reg + TCWAW_AND_ADDR_2_DATA); in denali_select_target()
223 iowrite32(sel->re_2_we, denali->reg + RE_2_WE); in denali_select_target()
224 iowrite32(sel->acc_clks, denali->reg + ACC_CLKS); in denali_select_target()
225 iowrite32(sel->rdwr_en_lo_cnt, denali->reg + RDWR_EN_LO_CNT); in denali_select_target()
226 iowrite32(sel->rdwr_en_hi_cnt, denali->reg + RDWR_EN_HI_CNT); in denali_select_target()
227 iowrite32(sel->cs_setup_cnt, denali->reg + CS_SETUP_CNT); in denali_select_target()
228 iowrite32(sel->re_2_re, denali->reg + RE_2_RE); in denali_select_target()
232 void *buf, unsigned int len, bool write) in denali_change_column() argument
235 return nand_change_write_column_op(chip, offset, buf, len, in denali_change_column()
238 return nand_change_read_column_op(chip, offset, buf, len, in denali_change_column()
246 struct nand_ecc_ctrl *ecc = &chip->ecc; in denali_payload_xfer()
247 int writesize = mtd->writesize; in denali_payload_xfer()
248 int oob_skip = denali->oob_skip_bytes; in denali_payload_xfer()
249 int ret, i, pos, len; in denali_payload_xfer() local
251 for (i = 0; i < ecc->steps; i++) { in denali_payload_xfer()
252 pos = i * (ecc->size + ecc->bytes); in denali_payload_xfer()
253 len = ecc->size; in denali_payload_xfer()
257 } else if (pos + len > writesize) { in denali_payload_xfer()
260 writesize - pos, write); in denali_payload_xfer()
264 buf += writesize - pos; in denali_payload_xfer()
265 len -= writesize - pos; in denali_payload_xfer()
269 ret = denali_change_column(chip, pos, buf, len, write); in denali_payload_xfer()
273 buf += len; in denali_payload_xfer()
283 struct nand_ecc_ctrl *ecc = &chip->ecc; in denali_oob_xfer()
284 int writesize = mtd->writesize; in denali_oob_xfer()
285 int oobsize = mtd->oobsize; in denali_oob_xfer()
286 int oob_skip = denali->oob_skip_bytes; in denali_oob_xfer()
287 int ret, i, pos, len; in denali_oob_xfer() local
296 for (i = 0; i < ecc->steps; i++) { in denali_oob_xfer()
297 pos = ecc->size + i * (ecc->size + ecc->bytes); in denali_oob_xfer()
299 if (i == ecc->steps - 1) in denali_oob_xfer()
301 len = writesize + oobsize - pos - oob_skip; in denali_oob_xfer()
303 len = ecc->bytes; in denali_oob_xfer()
307 } else if (pos + len > writesize) { in denali_oob_xfer()
310 writesize - pos, write); in denali_oob_xfer()
314 buf += writesize - pos; in denali_oob_xfer()
315 len -= writesize - pos; in denali_oob_xfer()
319 ret = denali_change_column(chip, pos, buf, len, write); in denali_oob_xfer()
323 buf += len; in denali_oob_xfer()
335 return -EINVAL; in denali_read_raw()
362 return -EINVAL; in denali_write_raw()
386 return denali_read_raw(chip, buf, oob_required ? chip->oob_poi : NULL, in denali_read_page_raw()
393 return denali_write_raw(chip, buf, oob_required ? chip->oob_poi : NULL, in denali_write_page_raw()
399 return denali_read_raw(chip, NULL, chip->oob_poi, page); in denali_read_oob()
404 return denali_write_raw(chip, NULL, chip->oob_poi, page); in denali_write_oob()
412 struct mtd_ecc_stats *ecc_stats = &nand_to_mtd(chip)->ecc_stats; in denali_check_erased_page()
413 struct nand_ecc_ctrl *ecc = &chip->ecc; in denali_check_erased_page()
414 u8 *ecc_code = chip->oob_poi + denali->oob_skip_bytes; in denali_check_erased_page()
417 for (i = 0; i < ecc->steps; i++) { in denali_check_erased_page()
421 stat = nand_check_erased_ecc_chunk(buf, ecc->size, ecc_code, in denali_check_erased_page()
422 ecc->bytes, NULL, 0, in denali_check_erased_page()
423 ecc->strength); in denali_check_erased_page()
425 ecc_stats->failed++; in denali_check_erased_page()
427 ecc_stats->corrected += stat; in denali_check_erased_page()
431 buf += ecc->size; in denali_check_erased_page()
432 ecc_code += ecc->bytes; in denali_check_erased_page()
442 struct mtd_ecc_stats *ecc_stats = &nand_to_mtd(chip)->ecc_stats; in denali_hw_ecc_fixup()
443 int bank = denali->active_bank; in denali_hw_ecc_fixup()
447 ecc_cor = ioread32(denali->reg + ECC_COR_INFO(bank)); in denali_hw_ecc_fixup()
454 * "which sector(s)". We need erase-page check for all sectors. in denali_hw_ecc_fixup()
456 *uncor_ecc_flags = GENMASK(chip->ecc.steps - 1, 0); in denali_hw_ecc_fixup()
463 * The register holds the maximum of per-sector corrected bitflips. in denali_hw_ecc_fixup()
464 * This is suitable for the return value of the ->read_page() callback. in denali_hw_ecc_fixup()
468 ecc_stats->corrected += max_bitflips; in denali_hw_ecc_fixup()
477 struct mtd_ecc_stats *ecc_stats = &nand_to_mtd(chip)->ecc_stats; in denali_sw_ecc_fixup()
478 unsigned int ecc_size = chip->ecc.size; in denali_sw_ecc_fixup()
490 err_addr = ioread32(denali->reg + ECC_ERROR_ADDRESS); in denali_sw_ecc_fixup()
494 err_cor_info = ioread32(denali->reg + ERR_CORRECTION_INFO); in denali_sw_ecc_fixup()
522 denali->devs_per_cs + err_device; in denali_sw_ecc_fixup()
527 ecc_stats->corrected += flips_in_byte; in denali_sw_ecc_fixup()
530 max_bitflips = max(max_bitflips, bitflips); in denali_sw_ecc_fixup()
542 return -EIO; in denali_sw_ecc_fixup()
559 * burst len = 64 bytes, the number of pages in denali_setup_dma64()
561 denali->host_write(denali, mode, in denali_setup_dma64()
566 denali->host_write(denali, mode, lower_32_bits(dma_addr)); in denali_setup_dma64()
569 denali->host_write(denali, mode, upper_32_bits(dma_addr)); in denali_setup_dma64()
583 denali->host_write(denali, mode | page, in denali_setup_dma32()
587 denali->host_write(denali, mode | ((dma_addr >> 16) << 8), 0x2200); in denali_setup_dma32()
590 denali->host_write(denali, mode | ((dma_addr & 0xffff) << 8), 0x2300); in denali_setup_dma32()
592 /* 4. interrupt when complete, burst len = 64 bytes */ in denali_setup_dma32()
593 denali->host_write(denali, mode | 0x14000, 0x2400); in denali_setup_dma32()
603 if (denali->caps & DENALI_CAP_HW_ECC_FIXUP) in denali_pio_read()
611 buf[i] = denali->host_read(denali, addr); in denali_pio_read()
615 return -EIO; in denali_pio_read()
620 return irq_status & ecc_err_mask ? -EBADMSG : 0; in denali_pio_read()
633 denali->host_write(denali, addr, buf[i]); in denali_pio_write()
639 return -EIO; in denali_pio_write()
661 dma_addr = dma_map_single(denali->dev, buf, size, dir); in denali_dma_xfer()
662 if (dma_mapping_error(denali->dev, dma_addr)) { in denali_dma_xfer()
663 dev_dbg(denali->dev, "Failed to DMA-map buffer. Trying PIO.\n"); in denali_dma_xfer()
675 } else if (denali->caps & DENALI_CAP_HW_ECC_FIXUP) { in denali_dma_xfer()
683 iowrite32(DMA_ENABLE__FLAG, denali->reg + DMA_ENABLE); in denali_dma_xfer()
685 * The ->setup_dma() hook kicks DMA by using the data/command in denali_dma_xfer()
686 * interface, which belongs to a different AXI port from the in denali_dma_xfer()
689 ioread32(denali->reg + DMA_ENABLE); in denali_dma_xfer()
692 denali->setup_dma(denali, dma_addr, page, write); in denali_dma_xfer()
696 ret = -EIO; in denali_dma_xfer()
698 ret = -EBADMSG; in denali_dma_xfer()
700 iowrite32(0, denali->reg + DMA_ENABLE); in denali_dma_xfer()
702 dma_unmap_single(denali->dev, dma_addr, size, dir); in denali_dma_xfer()
715 denali_select_target(chip, chip->cur_cs); in denali_page_xfer()
717 if (denali->dma_avail) in denali_page_xfer()
732 ret = denali_page_xfer(chip, buf, mtd->writesize, page, false); in denali_read_page()
733 if (ret && ret != -EBADMSG) in denali_read_page()
736 if (denali->caps & DENALI_CAP_HW_ECC_FIXUP) in denali_read_page()
738 else if (ret == -EBADMSG) in denali_read_page()
761 return denali_page_xfer(chip, (void *)buf, mtd->writesize, page, true); in denali_write_page()
782 t_x = DIV_ROUND_DOWN_ULL(1000000000000ULL, denali->clk_x_rate); in denali_setup_interface()
784 return -EINVAL; in denali_setup_interface()
791 mult_x = DIV_ROUND_CLOSEST_ULL(denali->clk_x_rate, denali->clk_rate); in denali_setup_interface()
793 return -EINVAL; in denali_setup_interface()
798 sel = &to_denali_chip(chip)->sels[chipnr]; in denali_setup_interface()
800 /* tRWH -> RE_2_WE */ in denali_setup_interface()
801 re_2_we = DIV_ROUND_UP(timings->tRHW_min, t_x); in denali_setup_interface()
804 tmp = ioread32(denali->reg + RE_2_WE); in denali_setup_interface()
807 sel->re_2_we = tmp; in denali_setup_interface()
809 /* tRHZ -> RE_2_RE */ in denali_setup_interface()
810 re_2_re = DIV_ROUND_UP(timings->tRHZ_max, t_x); in denali_setup_interface()
813 tmp = ioread32(denali->reg + RE_2_RE); in denali_setup_interface()
816 sel->re_2_re = tmp; in denali_setup_interface()
819 * tCCS, tWHR -> WE_2_RE in denali_setup_interface()
824 we_2_re = DIV_ROUND_UP(max(timings->tCCS_min, timings->tWHR_min), t_x); in denali_setup_interface()
827 tmp = ioread32(denali->reg + TWHR2_AND_WE_2_RE); in denali_setup_interface()
830 sel->hwhr2_and_we_2_re = tmp; in denali_setup_interface()
832 /* tADL -> ADDR_2_DATA */ in denali_setup_interface()
836 if (denali->revision < 0x0501) in denali_setup_interface()
839 addr_2_data = DIV_ROUND_UP(timings->tADL_min, t_x); in denali_setup_interface()
842 tmp = ioread32(denali->reg + TCWAW_AND_ADDR_2_DATA); in denali_setup_interface()
845 sel->tcwaw_and_addr_2_data = tmp; in denali_setup_interface()
847 /* tREH, tWH -> RDWR_EN_HI_CNT */ in denali_setup_interface()
848 rdwr_en_hi = DIV_ROUND_UP(max(timings->tREH_min, timings->tWH_min), in denali_setup_interface()
852 tmp = ioread32(denali->reg + RDWR_EN_HI_CNT); in denali_setup_interface()
855 sel->rdwr_en_hi_cnt = tmp; in denali_setup_interface()
858 * tREA -> ACC_CLKS in denali_setup_interface()
859 * tRP, tWP, tRHOH, tRC, tWC -> RDWR_EN_LO_CNT in denali_setup_interface()
866 * The delay on the chip side is well-defined as tREA, but we need to in denali_setup_interface()
871 acc_clks = DIV_ROUND_UP(timings->tREA_max + data_setup_on_host, t_x); in denali_setup_interface()
874 rdwr_en_lo = DIV_ROUND_UP(max(timings->tRP_min, timings->tWP_min), t_x); in denali_setup_interface()
878 acc_clks - timings->tRHOH_min / t_x); in denali_setup_interface()
881 rdwr_en_lo_hi = DIV_ROUND_UP(max(timings->tRC_min, timings->tWC_min), in denali_setup_interface()
883 rdwr_en_lo = max(rdwr_en_lo, rdwr_en_lo_hi - rdwr_en_hi); in denali_setup_interface()
888 DIV_ROUND_UP(timings->tRHOH_min, t_x)) / 2; in denali_setup_interface()
891 tmp = ioread32(denali->reg + ACC_CLKS); in denali_setup_interface()
894 sel->acc_clks = tmp; in denali_setup_interface()
896 tmp = ioread32(denali->reg + RDWR_EN_LO_CNT); in denali_setup_interface()
899 sel->rdwr_en_lo_cnt = tmp; in denali_setup_interface()
901 /* tCS, tCEA -> CS_SETUP_CNT */ in denali_setup_interface()
902 cs_setup = max3((int)DIV_ROUND_UP(timings->tCS_min, t_x) - rdwr_en_lo, in denali_setup_interface()
903 (int)DIV_ROUND_UP(timings->tCEA_max, t_x) - acc_clks, in denali_setup_interface()
907 tmp = ioread32(denali->reg + CS_SETUP_CNT); in denali_setup_interface()
910 sel->cs_setup_cnt = tmp; in denali_setup_interface()
929 return -ERANGE; in denali_ooblayout_ecc()
931 oobregion->offset = denali->oob_skip_bytes; in denali_ooblayout_ecc()
932 oobregion->length = chip->ecc.total; in denali_ooblayout_ecc()
944 return -ERANGE; in denali_ooblayout_free()
946 oobregion->offset = chip->ecc.total + denali->oob_skip_bytes; in denali_ooblayout_free()
947 oobregion->length = mtd->oobsize - oobregion->offset; in denali_ooblayout_free()
963 memorg = nanddev_get_memorg(&chip->base); in denali_multidev_fixup()
972 denali->devs_per_cs = ioread32(denali->reg + DEVICES_CONNECTED); in denali_multidev_fixup()
975 * On some SoCs, DEVICES_CONNECTED is not auto-detected. in denali_multidev_fixup()
978 if (denali->devs_per_cs == 0) { in denali_multidev_fixup()
979 denali->devs_per_cs = 1; in denali_multidev_fixup()
980 iowrite32(1, denali->reg + DEVICES_CONNECTED); in denali_multidev_fixup()
983 if (denali->devs_per_cs == 1) in denali_multidev_fixup()
986 if (denali->devs_per_cs != 2) { in denali_multidev_fixup()
987 dev_err(denali->dev, "unsupported number of devices %d\n", in denali_multidev_fixup()
988 denali->devs_per_cs); in denali_multidev_fixup()
989 return -EINVAL; in denali_multidev_fixup()
993 memorg->pagesize <<= 1; in denali_multidev_fixup()
994 memorg->oobsize <<= 1; in denali_multidev_fixup()
995 mtd->size <<= 1; in denali_multidev_fixup()
996 mtd->erasesize <<= 1; in denali_multidev_fixup()
997 mtd->writesize <<= 1; in denali_multidev_fixup()
998 mtd->oobsize <<= 1; in denali_multidev_fixup()
999 chip->page_shift += 1; in denali_multidev_fixup()
1000 chip->phys_erase_shift += 1; in denali_multidev_fixup()
1001 chip->bbt_erase_shift += 1; in denali_multidev_fixup()
1002 chip->chip_shift += 1; in denali_multidev_fixup()
1003 chip->pagemask <<= 1; in denali_multidev_fixup()
1004 chip->ecc.size <<= 1; in denali_multidev_fixup()
1005 chip->ecc.bytes <<= 1; in denali_multidev_fixup()
1006 chip->ecc.strength <<= 1; in denali_multidev_fixup()
1007 denali->oob_skip_bytes <<= 1; in denali_multidev_fixup()
1018 ret = nand_ecc_choose_conf(chip, denali->ecc_caps, in denali_attach_chip()
1019 mtd->oobsize - denali->oob_skip_bytes); in denali_attach_chip()
1021 dev_err(denali->dev, "Failed to setup ECC settings.\n"); in denali_attach_chip()
1025 dev_dbg(denali->dev, in denali_attach_chip()
1027 chip->ecc.size, chip->ecc.strength, chip->ecc.bytes); in denali_attach_chip()
1037 u8 *buf, unsigned int len) in denali_exec_in8() argument
1041 for (i = 0; i < len; i++) in denali_exec_in8()
1042 buf[i] = denali->host_read(denali, type | DENALI_BANK(denali)); in denali_exec_in8()
1046 u8 *buf, unsigned int len) in denali_exec_in16() argument
1051 for (i = 0; i < len; i += 2) { in denali_exec_in16()
1052 data = denali->host_read(denali, type | DENALI_BANK(denali)); in denali_exec_in16()
1060 u8 *buf, unsigned int len, bool width16) in denali_exec_in() argument
1063 denali_exec_in16(denali, type, buf, len); in denali_exec_in()
1065 denali_exec_in8(denali, type, buf, len); in denali_exec_in()
1069 const u8 *buf, unsigned int len) in denali_exec_out8() argument
1073 for (i = 0; i < len; i++) in denali_exec_out8()
1074 denali->host_write(denali, type | DENALI_BANK(denali), buf[i]); in denali_exec_out8()
1078 const u8 *buf, unsigned int len) in denali_exec_out16() argument
1082 for (i = 0; i < len; i += 2) in denali_exec_out16()
1083 denali->host_write(denali, type | DENALI_BANK(denali), in denali_exec_out16()
1088 const u8 *buf, unsigned int len, bool width16) in denali_exec_out() argument
1091 denali_exec_out16(denali, type, buf, len); in denali_exec_out()
1093 denali_exec_out8(denali, type, buf, len); in denali_exec_out()
1106 return irq_stat & INTR__INT_ACT ? 0 : -EIO; in denali_exec_waitrdy()
1114 switch (instr->type) { in denali_exec_instr()
1117 &instr->ctx.cmd.opcode, 1); in denali_exec_instr()
1121 instr->ctx.addr.addrs, in denali_exec_instr()
1122 instr->ctx.addr.naddrs); in denali_exec_instr()
1126 instr->ctx.data.buf.in, in denali_exec_instr()
1127 instr->ctx.data.len, in denali_exec_instr()
1128 !instr->ctx.data.force_8bit && in denali_exec_instr()
1129 chip->options & NAND_BUSWIDTH_16); in denali_exec_instr()
1133 instr->ctx.data.buf.out, in denali_exec_instr()
1134 instr->ctx.data.len, in denali_exec_instr()
1135 !instr->ctx.data.force_8bit && in denali_exec_instr()
1136 chip->options & NAND_BUSWIDTH_16); in denali_exec_instr()
1142 instr->type); in denali_exec_instr()
1144 return -EINVAL; in denali_exec_instr()
1156 denali_select_target(chip, op->cs); in denali_exec_op()
1164 for (i = 0; i < op->ninstrs; i++) { in denali_exec_op()
1165 ret = denali_exec_instr(chip, &op->instrs[i]); in denali_exec_op()
1182 struct nand_chip *chip = &dchip->chip; in denali_chip_init()
1187 chip->controller = &denali->controller; in denali_chip_init()
1190 for (i = 0; i < dchip->nsels; i++) { in denali_chip_init()
1191 unsigned int bank = dchip->sels[i].bank; in denali_chip_init()
1193 if (bank >= denali->nbanks) { in denali_chip_init()
1194 dev_err(denali->dev, "unsupported bank %d\n", bank); in denali_chip_init()
1195 return -EINVAL; in denali_chip_init()
1199 if (bank == dchip->sels[j].bank) { in denali_chip_init()
1200 dev_err(denali->dev, in denali_chip_init()
1203 return -EINVAL; in denali_chip_init()
1207 list_for_each_entry(dchip2, &denali->chips, node) { in denali_chip_init()
1208 for (j = 0; j < dchip2->nsels; j++) { in denali_chip_init()
1209 if (bank == dchip2->sels[j].bank) { in denali_chip_init()
1210 dev_err(denali->dev, in denali_chip_init()
1213 return -EINVAL; in denali_chip_init()
1219 mtd->dev.parent = denali->dev; in denali_chip_init()
1225 if (!mtd->name && list_empty(&denali->chips)) in denali_chip_init()
1226 mtd->name = "denali-nand"; in denali_chip_init()
1228 if (denali->dma_avail) { in denali_chip_init()
1229 chip->options |= NAND_USES_DMA; in denali_chip_init()
1230 chip->buf_align = 16; in denali_chip_init()
1234 if (!denali->clk_rate || !denali->clk_x_rate) in denali_chip_init()
1235 chip->options |= NAND_KEEP_TIMINGS; in denali_chip_init()
1237 chip->bbt_options |= NAND_BBT_USE_FLASH; in denali_chip_init()
1238 chip->bbt_options |= NAND_BBT_NO_OOB; in denali_chip_init()
1239 chip->options |= NAND_NO_SUBPAGE_WRITE; in denali_chip_init()
1240 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; in denali_chip_init()
1241 chip->ecc.placement = NAND_ECC_PLACEMENT_INTERLEAVED; in denali_chip_init()
1242 chip->ecc.read_page = denali_read_page; in denali_chip_init()
1243 chip->ecc.write_page = denali_write_page; in denali_chip_init()
1244 chip->ecc.read_page_raw = denali_read_page_raw; in denali_chip_init()
1245 chip->ecc.write_page_raw = denali_write_page_raw; in denali_chip_init()
1246 chip->ecc.read_oob = denali_read_oob; in denali_chip_init()
1247 chip->ecc.write_oob = denali_write_oob; in denali_chip_init()
1251 ret = nand_scan(chip, dchip->nsels); in denali_chip_init()
1257 dev_err(denali->dev, "Failed to register MTD: %d\n", ret); in denali_chip_init()
1261 list_add_tail(&dchip->node, &denali->chips); in denali_chip_init()
1274 u32 features = ioread32(denali->reg + FEATURES); in denali_init()
1277 nand_controller_init(&denali->controller); in denali_init()
1278 denali->controller.ops = &denali_controller_ops; in denali_init()
1279 init_completion(&denali->complete); in denali_init()
1280 spin_lock_init(&denali->irq_lock); in denali_init()
1281 INIT_LIST_HEAD(&denali->chips); in denali_init()
1282 denali->active_bank = DENALI_INVALID_BANK; in denali_init()
1288 if (!denali->revision) in denali_init()
1289 denali->revision = swab16(ioread32(denali->reg + REVISION)); in denali_init()
1291 denali->nbanks = 1 << FIELD_GET(FEATURES__N_BANKS, features); in denali_init()
1294 if (denali->revision < 0x0501) in denali_init()
1295 denali->nbanks <<= 1; in denali_init()
1298 denali->dma_avail = true; in denali_init()
1300 if (denali->dma_avail) { in denali_init()
1301 int dma_bit = denali->caps & DENALI_CAP_DMA_64BIT ? 64 : 32; in denali_init()
1303 ret = dma_set_mask(denali->dev, DMA_BIT_MASK(dma_bit)); in denali_init()
1305 dev_info(denali->dev, in denali_init()
1307 denali->dma_avail = false; in denali_init()
1311 if (denali->dma_avail) { in denali_init()
1312 if (denali->caps & DENALI_CAP_DMA_64BIT) in denali_init()
1313 denali->setup_dma = denali_setup_dma64; in denali_init()
1315 denali->setup_dma = denali_setup_dma32; in denali_init()
1319 denali->host_read = denali_indexed_read; in denali_init()
1320 denali->host_write = denali_indexed_write; in denali_init()
1322 denali->host_read = denali_direct_read; in denali_init()
1323 denali->host_write = denali_direct_write; in denali_init()
1328 * If a platform requests a non-zero value, set it to the register. in denali_init()
1332 if (denali->oob_skip_bytes) in denali_init()
1333 iowrite32(denali->oob_skip_bytes, in denali_init()
1334 denali->reg + SPARE_AREA_SKIP_BYTES); in denali_init()
1336 denali->oob_skip_bytes = ioread32(denali->reg + in denali_init()
1339 iowrite32(0, denali->reg + TRANSFER_SPARE_REG); in denali_init()
1340 iowrite32(GENMASK(denali->nbanks - 1, 0), denali->reg + RB_PIN_ENABLED); in denali_init()
1341 iowrite32(CHIP_EN_DONT_CARE__FLAG, denali->reg + CHIP_ENABLE_DONT_CARE); in denali_init()
1342 iowrite32(ECC_ENABLE__FLAG, denali->reg + ECC_ENABLE); in denali_init()
1343 iowrite32(0xffff, denali->reg + SPARE_AREA_MARKER); in denali_init()
1344 iowrite32(WRITE_PROTECT__FLAG, denali->reg + WRITE_PROTECT); in denali_init()
1348 ret = devm_request_irq(denali->dev, denali->irq, denali_isr, in denali_init()
1351 dev_err(denali->dev, "Unable to request IRQ\n"); in denali_init()
1367 list_for_each_entry_safe(dchip, tmp, &denali->chips, node) { in denali_remove()
1368 chip = &dchip->chip; in denali_remove()
1372 list_del(&dchip->node); in denali_remove()