Lines Matching +full:nand +full:- +full:ecc +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * davinci_nand.c - NAND Flash Driver for DaVinci family chips
8 * Sander Huijsen <Shuijsen@optelecom-nkf.com>
28 /* 4-bit ECC syndrome registers */
40 * for ALE/CLE unless they support booting from NAND.
51 * 0-indexed chip-select number of the asynchronous
52 * interface to which the NAND device has been connected.
54 * So, if you have NAND connected to CS3 of DA850, you
71 * All DaVinci-family chips support 1-bit hardware ECC.
72 * Newer ones also support 4-bit ECC, but are awkward
90 * This is a device driver for the NAND flash controller found on the
95 * The 1-bit ECC hardware is supported, as well as the newer 4-bit ECC
96 * available on chips like the DM355 and OMAP-L137 and needed with the
97 * more error-prone MLC NAND chips.
99 * This driver assumes EM_WAIT connects all the NAND devices' RDY/nBUSY
100 * outputs in a "wire-AND" configuration, with no per-chip signals.
133 return __raw_readl(info->base + offset); in davinci_nand_readl()
139 __raw_writel(value, info->base + offset); in davinci_nand_writel()
142 /*----------------------------------------------------------------------*/
145 * 1-bit hardware ECC ... context maintained for each core chipselect
153 + 4 * info->core_chipsel); in nand_davinci_readecc_1bit()
156 static void nand_davinci_hwctl_1bit(struct nand_chip *chip, int mode) in nand_davinci_hwctl_1bit() argument
164 /* Reset ECC hardware */ in nand_davinci_hwctl_1bit()
169 /* Restart ECC hardware */ in nand_davinci_hwctl_1bit()
171 nandcfr |= BIT(8 + info->core_chipsel); in nand_davinci_hwctl_1bit()
178 * Read hardware ECC value and pack into three bytes
186 /* invert so that erased block ecc is correct */ in nand_davinci_calculate_1bit()
207 if ((diff >> (12 + 3)) < chip->ecc.size) { in nand_davinci_correct_1bit()
211 return -EBADMSG; in nand_davinci_correct_1bit()
213 } else if (!(diff & (diff - 1))) { in nand_davinci_correct_1bit()
214 /* Single bit ECC error in the ECC itself, in nand_davinci_correct_1bit()
219 return -EBADMSG; in nand_davinci_correct_1bit()
226 /*----------------------------------------------------------------------*/
229 * 4-bit hardware ECC ... context maintained over entire AEMIF
234 * Also, and specific to this hardware, it ECC-protects the "prepad"
235 * in the OOB ... while having ECC protection for parts of OOB would
237 * OOB without recomputing ECC.
240 static void nand_davinci_hwctl_4bit(struct nand_chip *chip, int mode) in nand_davinci_hwctl_4bit() argument
246 /* Reset ECC hardware */ in nand_davinci_hwctl_4bit()
251 /* Start 4-bit ECC calculation for read/write */ in nand_davinci_hwctl_4bit()
254 val |= (info->core_chipsel << 4) | BIT(12); in nand_davinci_hwctl_4bit()
257 info->is_readmode = (mode == NAND_ECC_READ); in nand_davinci_hwctl_4bit()
262 /* Read raw ECC code after writing to NAND. */
274 /* Terminate read ECC; or return ECC (as bytes) of data written to NAND. */
282 /* After a read, terminate ECC calculation by a dummy read in nand_davinci_calculate_4bit()
283 * of some 4-bit ECC register. ECC covers everything that in nand_davinci_calculate_4bit()
287 if (info->is_readmode) { in nand_davinci_calculate_4bit()
292 /* Pack eight raw 10-bit ecc values into ten bytes, making in nand_davinci_calculate_4bit()
294 * lower halves of two 32-bit words) into five bytes. The in nand_davinci_calculate_4bit()
325 * little-endian, and use type punning for less shifting/masking. in nand_davinci_correct_4bit()
328 return -EINVAL; in nand_davinci_correct_4bit()
340 /* Tell ECC controller about the expected ECC codes. */ in nand_davinci_correct_4bit()
341 for (i = 7; i >= 0; i--) in nand_davinci_correct_4bit()
371 * long as ECC_STATE reads less than 4. After that, ECC HW has entered in nand_davinci_correct_4bit()
390 return -EBADMSG; in nand_davinci_correct_4bit()
423 error_address = (512 + 7) - error_address; in nand_davinci_correct_4bit()
434 /*----------------------------------------------------------------------*/
436 /* An ECC layout for using 4-bit ECC with small-page flash, storing
437 * ten ECC bytes plus the manufacturer's bad block marker byte, and
444 return -ERANGE; in hwecc4_ooblayout_small_ecc()
447 oobregion->offset = 0; in hwecc4_ooblayout_small_ecc()
448 oobregion->length = 5; in hwecc4_ooblayout_small_ecc()
450 oobregion->offset = 6; in hwecc4_ooblayout_small_ecc()
451 oobregion->length = 2; in hwecc4_ooblayout_small_ecc()
453 oobregion->offset = 13; in hwecc4_ooblayout_small_ecc()
454 oobregion->length = 3; in hwecc4_ooblayout_small_ecc()
464 return -ERANGE; in hwecc4_ooblayout_small_free()
467 oobregion->offset = 8; in hwecc4_ooblayout_small_free()
468 oobregion->length = 5; in hwecc4_ooblayout_small_free()
470 oobregion->offset = 16; in hwecc4_ooblayout_small_free()
471 oobregion->length = mtd->oobsize - 16; in hwecc4_ooblayout_small_free()
478 .ecc = hwecc4_ooblayout_small_ecc,
484 {.compatible = "ti,davinci-nand", },
485 {.compatible = "ti,keystone-nand", },
493 if (!dev_get_platdata(&pdev->dev) && pdev->dev.of_node) { in nand_davinci_get_pdata()
495 const char *mode; in nand_davinci_get_pdata() local
498 pdata = devm_kzalloc(&pdev->dev, in nand_davinci_get_pdata()
501 pdev->dev.platform_data = pdata; in nand_davinci_get_pdata()
503 return ERR_PTR(-ENOMEM); in nand_davinci_get_pdata()
504 if (!of_property_read_u32(pdev->dev.of_node, in nand_davinci_get_pdata()
505 "ti,davinci-chipselect", &prop)) in nand_davinci_get_pdata()
506 pdata->core_chipsel = prop; in nand_davinci_get_pdata()
508 return ERR_PTR(-EINVAL); in nand_davinci_get_pdata()
510 if (!of_property_read_u32(pdev->dev.of_node, in nand_davinci_get_pdata()
511 "ti,davinci-mask-ale", &prop)) in nand_davinci_get_pdata()
512 pdata->mask_ale = prop; in nand_davinci_get_pdata()
513 if (!of_property_read_u32(pdev->dev.of_node, in nand_davinci_get_pdata()
514 "ti,davinci-mask-cle", &prop)) in nand_davinci_get_pdata()
515 pdata->mask_cle = prop; in nand_davinci_get_pdata()
516 if (!of_property_read_u32(pdev->dev.of_node, in nand_davinci_get_pdata()
517 "ti,davinci-mask-chipsel", &prop)) in nand_davinci_get_pdata()
518 pdata->mask_chipsel = prop; in nand_davinci_get_pdata()
519 if (!of_property_read_string(pdev->dev.of_node, in nand_davinci_get_pdata()
520 "ti,davinci-ecc-mode", &mode)) { in nand_davinci_get_pdata()
521 if (!strncmp("none", mode, 4)) in nand_davinci_get_pdata()
522 pdata->engine_type = NAND_ECC_ENGINE_TYPE_NONE; in nand_davinci_get_pdata()
523 if (!strncmp("soft", mode, 4)) in nand_davinci_get_pdata()
524 pdata->engine_type = NAND_ECC_ENGINE_TYPE_SOFT; in nand_davinci_get_pdata()
525 if (!strncmp("hw", mode, 2)) in nand_davinci_get_pdata()
526 pdata->engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; in nand_davinci_get_pdata()
528 if (!of_property_read_u32(pdev->dev.of_node, in nand_davinci_get_pdata()
529 "ti,davinci-ecc-bits", &prop)) in nand_davinci_get_pdata()
530 pdata->ecc_bits = prop; in nand_davinci_get_pdata()
532 if (!of_property_read_u32(pdev->dev.of_node, in nand_davinci_get_pdata()
533 "ti,davinci-nand-buswidth", &prop) && prop == 16) in nand_davinci_get_pdata()
534 pdata->options |= NAND_BUSWIDTH_16; in nand_davinci_get_pdata()
536 if (of_property_read_bool(pdev->dev.of_node, in nand_davinci_get_pdata()
537 "ti,davinci-nand-use-bbt")) in nand_davinci_get_pdata()
538 pdata->bbt_options = NAND_BBT_USE_FLASH; in nand_davinci_get_pdata()
542 * use of 4-bit hardware ECC with subpages and verified on in nand_davinci_get_pdata()
545 * existing UBI partitions, sub-page writes are not being in nand_davinci_get_pdata()
548 * then use "ti,davinci-nand" as the compatible in your in nand_davinci_get_pdata()
549 * device-tree file. in nand_davinci_get_pdata()
551 if (of_device_is_compatible(pdev->dev.of_node, in nand_davinci_get_pdata()
552 "ti,keystone-nand")) { in nand_davinci_get_pdata()
553 pdata->options |= NAND_NO_SUBPAGE_WRITE; in nand_davinci_get_pdata()
557 return dev_get_platdata(&pdev->dev); in nand_davinci_get_pdata()
563 return dev_get_platdata(&pdev->dev); in nand_davinci_get_pdata()
571 struct davinci_nand_pdata *pdata = nand_davinci_get_pdata(info->pdev); in davinci_nand_attach_chip()
577 /* Use board-specific ECC config */ in davinci_nand_attach_chip()
578 chip->ecc.engine_type = pdata->engine_type; in davinci_nand_attach_chip()
579 chip->ecc.placement = pdata->ecc_placement; in davinci_nand_attach_chip()
581 switch (chip->ecc.engine_type) { in davinci_nand_attach_chip()
583 pdata->ecc_bits = 0; in davinci_nand_attach_chip()
586 pdata->ecc_bits = 0; in davinci_nand_attach_chip()
588 * This driver expects Hamming based ECC when engine_type is set in davinci_nand_attach_chip()
589 * to NAND_ECC_ENGINE_TYPE_SOFT. Force ecc.algo to in davinci_nand_attach_chip()
590 * NAND_ECC_ALGO_HAMMING to avoid adding an extra ->ecc_algo in davinci_nand_attach_chip()
593 chip->ecc.algo = NAND_ECC_ALGO_HAMMING; in davinci_nand_attach_chip()
596 if (pdata->ecc_bits == 4) { in davinci_nand_attach_chip()
597 int chunks = mtd->writesize / 512; in davinci_nand_attach_chip()
599 if (!chunks || mtd->oobsize < 16) { in davinci_nand_attach_chip()
600 dev_dbg(&info->pdev->dev, "too small\n"); in davinci_nand_attach_chip()
601 return -EINVAL; in davinci_nand_attach_chip()
609 /* No sharing 4-bit hardware between chipselects yet */ in davinci_nand_attach_chip()
612 ret = -EBUSY; in davinci_nand_attach_chip()
617 if (ret == -EBUSY) in davinci_nand_attach_chip()
620 chip->ecc.calculate = nand_davinci_calculate_4bit; in davinci_nand_attach_chip()
621 chip->ecc.correct = nand_davinci_correct_4bit; in davinci_nand_attach_chip()
622 chip->ecc.hwctl = nand_davinci_hwctl_4bit; in davinci_nand_attach_chip()
623 chip->ecc.bytes = 10; in davinci_nand_attach_chip()
624 chip->ecc.options = NAND_ECC_GENERIC_ERASED_CHECK; in davinci_nand_attach_chip()
625 chip->ecc.algo = NAND_ECC_ALGO_BCH; in davinci_nand_attach_chip()
628 * Update ECC layout if needed ... for 1-bit HW ECC, the in davinci_nand_attach_chip()
630 * are needed (for each 512 bytes). For 4-bit HW ECC, in davinci_nand_attach_chip()
643 chip->ecc.read_page = nand_read_page_hwecc_oob_first; in davinci_nand_attach_chip()
645 return -EIO; in davinci_nand_attach_chip()
648 /* 1bit ecc hamming */ in davinci_nand_attach_chip()
649 chip->ecc.calculate = nand_davinci_calculate_1bit; in davinci_nand_attach_chip()
650 chip->ecc.correct = nand_davinci_correct_1bit; in davinci_nand_attach_chip()
651 chip->ecc.hwctl = nand_davinci_hwctl_1bit; in davinci_nand_attach_chip()
652 chip->ecc.bytes = 3; in davinci_nand_attach_chip()
653 chip->ecc.algo = NAND_ECC_ALGO_HAMMING; in davinci_nand_attach_chip()
655 chip->ecc.size = 512; in davinci_nand_attach_chip()
656 chip->ecc.strength = pdata->ecc_bits; in davinci_nand_attach_chip()
659 return -EINVAL; in davinci_nand_attach_chip()
671 ioread8_rep(info->current_cs, buf, len); in nand_davinci_data_in()
673 ioread16_rep(info->current_cs, buf, len >> 1); in nand_davinci_data_in()
675 ioread32_rep(info->current_cs, buf, len >> 2); in nand_davinci_data_in()
685 iowrite8_rep(info->current_cs, buf, len); in nand_davinci_data_out()
687 iowrite16_rep(info->current_cs, buf, len >> 1); in nand_davinci_data_out()
689 iowrite32_rep(info->current_cs, buf, len >> 2); in nand_davinci_data_out()
699 switch (instr->type) { in davinci_nand_exec_instr()
701 iowrite8(instr->ctx.cmd.opcode, in davinci_nand_exec_instr()
702 info->current_cs + info->mask_cle); in davinci_nand_exec_instr()
706 for (i = 0; i < instr->ctx.addr.naddrs; i++) { in davinci_nand_exec_instr()
707 iowrite8(instr->ctx.addr.addrs[i], in davinci_nand_exec_instr()
708 info->current_cs + info->mask_ale); in davinci_nand_exec_instr()
713 nand_davinci_data_in(info, instr->ctx.data.buf.in, in davinci_nand_exec_instr()
714 instr->ctx.data.len, in davinci_nand_exec_instr()
715 instr->ctx.data.force_8bit); in davinci_nand_exec_instr()
719 nand_davinci_data_out(info, instr->ctx.data.buf.out, in davinci_nand_exec_instr()
720 instr->ctx.data.len, in davinci_nand_exec_instr()
721 instr->ctx.data.force_8bit); in davinci_nand_exec_instr()
725 timeout_us = instr->ctx.waitrdy.timeout_ms * 1000; in davinci_nand_exec_instr()
726 ret = readl_relaxed_poll_timeout(info->base + NANDFSR_OFFSET, in davinci_nand_exec_instr()
735 if (instr->delay_ns) { in davinci_nand_exec_instr()
738 ndelay(instr->delay_ns); in davinci_nand_exec_instr()
754 info->current_cs = info->vaddr + (op->cs * info->mask_chipsel); in davinci_nand_exec_op()
756 for (i = 0; i < op->ninstrs; i++) { in davinci_nand_exec_op()
759 ret = davinci_nand_exec_instr(info, &op->instrs[i]); in davinci_nand_exec_op()
788 /* insist on board-specific configuration */ in nand_davinci_probe()
790 return -ENODEV; in nand_davinci_probe()
793 if (pdata->core_chipsel > 3) in nand_davinci_probe()
794 return -ENODEV; in nand_davinci_probe()
796 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); in nand_davinci_probe()
798 return -ENOMEM; in nand_davinci_probe()
805 dev_err(&pdev->dev, "resource missing\n"); in nand_davinci_probe()
806 return -EINVAL; in nand_davinci_probe()
809 vaddr = devm_ioremap_resource(&pdev->dev, res1); in nand_davinci_probe()
814 * This registers range is used to setup NAND settings. In case with in nand_davinci_probe()
817 * The AEMIF and NAND drivers not use the same registers in this range. in nand_davinci_probe()
819 base = devm_ioremap(&pdev->dev, res2->start, resource_size(res2)); in nand_davinci_probe()
821 dev_err(&pdev->dev, "ioremap failed for resource %pR\n", res2); in nand_davinci_probe()
822 return -EADDRNOTAVAIL; in nand_davinci_probe()
825 info->pdev = pdev; in nand_davinci_probe()
826 info->base = base; in nand_davinci_probe()
827 info->vaddr = vaddr; in nand_davinci_probe()
829 mtd = nand_to_mtd(&info->chip); in nand_davinci_probe()
830 mtd->dev.parent = &pdev->dev; in nand_davinci_probe()
831 nand_set_flash_node(&info->chip, pdev->dev.of_node); in nand_davinci_probe()
834 info->chip.bbt_options = pdata->bbt_options; in nand_davinci_probe()
835 /* options such as 16-bit widths */ in nand_davinci_probe()
836 info->chip.options = pdata->options; in nand_davinci_probe()
837 info->chip.bbt_td = pdata->bbt_td; in nand_davinci_probe()
838 info->chip.bbt_md = pdata->bbt_md; in nand_davinci_probe()
840 info->current_cs = info->vaddr; in nand_davinci_probe()
841 info->core_chipsel = pdata->core_chipsel; in nand_davinci_probe()
842 info->mask_chipsel = pdata->mask_chipsel; in nand_davinci_probe()
844 /* use nandboot-capable ALE/CLE masks by default */ in nand_davinci_probe()
845 info->mask_ale = pdata->mask_ale ? : MASK_ALE; in nand_davinci_probe()
846 info->mask_cle = pdata->mask_cle ? : MASK_CLE; in nand_davinci_probe()
850 /* put CSxNAND into NAND mode */ in nand_davinci_probe()
852 val |= BIT(info->core_chipsel); in nand_davinci_probe()
858 nand_controller_init(&info->controller); in nand_davinci_probe()
859 info->controller.ops = &davinci_nand_controller_ops; in nand_davinci_probe()
860 info->chip.controller = &info->controller; in nand_davinci_probe()
861 ret = nand_scan(&info->chip, pdata->mask_chipsel ? 2 : 1); in nand_davinci_probe()
863 dev_dbg(&pdev->dev, "no NAND chip(s) found\n"); in nand_davinci_probe()
867 if (pdata->parts) in nand_davinci_probe()
868 ret = mtd_device_register(mtd, pdata->parts, pdata->nr_parts); in nand_davinci_probe()
875 dev_info(&pdev->dev, "controller rev. %d.%d\n", in nand_davinci_probe()
881 nand_cleanup(&info->chip); in nand_davinci_probe()
889 struct nand_chip *chip = &info->chip; in nand_davinci_remove()
893 if (chip->ecc.placement == NAND_ECC_PLACEMENT_INTERLEAVED) in nand_davinci_remove()
916 MODULE_DESCRIPTION("Davinci NAND flash driver");