1 // SPDX-License-Identifier: GPL-2.0-only
9  *   This is a device driver for the NAND flash controller found on
11  *   mtd-id for command line partitioning is cs553x_nand_cs[0-3]
12  *   where 0-3 reflects the chip select for NAND.
34 #define MSR_NANDF_DATA		0x5140001b	/* NAND Flash Data Timing MSR */
54 /* Registers within the NAND flash controller BAR -- memory mapped */
56 #define MM_NAND_CTL		0x800	/* Any even address 0x800-0x80e */
57 #define MM_NAND_IO		0x801	/* Any odd address 0x801-0x80f */
65 /* Registers within the NAND flash controller BAR -- I/O mapped */
98 to_cs553x(struct nand_controller *controller)  in to_cs553x()  argument
100 	return container_of(controller, struct cs553x_nand_controller, base);  in to_cs553x()
104 				  u32 ctl, u8 data)  in cs553x_write_ctrl_byte()  argument
108 	writeb(ctl, cs553x->mmio + MM_NAND_CTL);  in cs553x_write_ctrl_byte()
109 	writeb(data, cs553x->mmio + MM_NAND_IO);  in cs553x_write_ctrl_byte()
110 	return readb_poll_timeout_atomic(cs553x->mmio + MM_NAND_STS, status,  in cs553x_write_ctrl_byte()
118 	writeb(0, cs553x->mmio + MM_NAND_CTL);  in cs553x_data_in()
120 		memcpy_fromio(buf, cs553x->mmio, 0x800);  in cs553x_data_in()
122 		len -= 0x800;  in cs553x_data_in()
124 	memcpy_fromio(buf, cs553x->mmio, len);  in cs553x_data_in()
130 	writeb(0, cs553x->mmio + MM_NAND_CTL);  in cs553x_data_out()
132 		memcpy_toio(cs553x->mmio, buf, 0x800);  in cs553x_data_out()
134 		len -= 0x800;  in cs553x_data_out()
136 	memcpy_toio(cs553x->mmio, buf, len);  in cs553x_data_out()
145 	return readb_poll_timeout(cs553x->mmio + MM_NAND_STS, status,  in cs553x_wait_ready()
156 	switch (instr->type) {  in cs553x_exec_instr()
159 					     instr->ctx.cmd.opcode);  in cs553x_exec_instr()
163 		for (i = 0; i < instr->ctx.addr.naddrs; i++) {  in cs553x_exec_instr()
165 						     instr->ctx.addr.addrs[i]);  in cs553x_exec_instr()
172 		cs553x_data_in(cs553x, instr->ctx.data.buf.in,  in cs553x_exec_instr()
173 			       instr->ctx.data.len);  in cs553x_exec_instr()
177 		cs553x_data_out(cs553x, instr->ctx.data.buf.out,  in cs553x_exec_instr()
178 				instr->ctx.data.len);  in cs553x_exec_instr()
182 		ret = cs553x_wait_ready(cs553x, instr->ctx.waitrdy.timeout_ms);  in cs553x_exec_instr()
186 	if (instr->delay_ns)  in cs553x_exec_instr()
187 		ndelay(instr->delay_ns);  in cs553x_exec_instr()
196 	struct cs553x_nand_controller *cs553x = to_cs553x(this->controller);  in cs553x_exec_op()
203 	/* De-assert the CE pin */  in cs553x_exec_op()
204 	writeb(0, cs553x->mmio + MM_NAND_CTL);  in cs553x_exec_op()
205 	for (i = 0; i < op->ninstrs; i++) {  in cs553x_exec_op()
206 		ret = cs553x_exec_instr(cs553x, &op->instrs[i]);  in cs553x_exec_op()
211 	/* Re-assert the CE pin. */  in cs553x_exec_op()
212 	writeb(CS_NAND_CTL_CE, cs553x->mmio + MM_NAND_CTL);  in cs553x_exec_op()
219 	struct cs553x_nand_controller *cs553x = to_cs553x(this->controller);  in cs_enable_hwecc()
221 	writeb(0x07, cs553x->mmio + MM_NAND_ECC_CTL);  in cs_enable_hwecc()
227 	struct cs553x_nand_controller *cs553x = to_cs553x(this->controller);  in cs_calculate_ecc()
230 	ecc = readl(cs553x->mmio + MM_NAND_STS);  in cs_calculate_ecc()
242 	if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST)  in cs553x_attach_chip()
245 	chip->ecc.size = 256;  in cs553x_attach_chip()
246 	chip->ecc.bytes = 3;  in cs553x_attach_chip()
247 	chip->ecc.hwctl  = cs_enable_hwecc;  in cs553x_attach_chip()
248 	chip->ecc.calculate = cs_calculate_ecc;  in cs553x_attach_chip()
249 	chip->ecc.correct  = rawnand_sw_hamming_correct;  in cs553x_attach_chip()
250 	chip->ecc.strength = 1;  in cs553x_attach_chip()
262 	struct cs553x_nand_controller *controller;  in cs553x_init_one()  local
267 	pr_notice("Probing CS553x NAND controller CS#%d at %sIO 0x%08lx\n",  in cs553x_init_one()
271 		pr_notice("PIO mode not yet implemented for CS553X NAND controller\n");  in cs553x_init_one()
272 		return -ENXIO;  in cs553x_init_one()
275 	/* Allocate memory for MTD device structure and private data */  in cs553x_init_one()
276 	controller = kzalloc(sizeof(*controller), GFP_KERNEL);  in cs553x_init_one()
277 	if (!controller) {  in cs553x_init_one()
278 		err = -ENOMEM;  in cs553x_init_one()
282 	this = &controller->chip;  in cs553x_init_one()
283 	nand_controller_init(&controller->base);  in cs553x_init_one()
284 	controller->base.ops = &cs553x_nand_controller_ops;  in cs553x_init_one()
285 	this->controller = &controller->base;  in cs553x_init_one()
288 	/* Link the private data with the MTD structure */  in cs553x_init_one()
289 	new_mtd->owner = THIS_MODULE;  in cs553x_init_one()
292 	controller->mmio = ioremap(adr, 4096);  in cs553x_init_one()
293 	if (!controller->mmio) {  in cs553x_init_one()
295 		err = -EIO;  in cs553x_init_one()
300 	this->bbt_options = NAND_BBT_USE_FLASH;  in cs553x_init_one()
302 	new_mtd->name = kasprintf(GFP_KERNEL, "cs553x_nand_cs%d", cs);  in cs553x_init_one()
303 	if (!new_mtd->name) {  in cs553x_init_one()
304 		err = -ENOMEM;  in cs553x_init_one()
313 	controllers[cs] = controller;  in cs553x_init_one()
317 	kfree(new_mtd->name);  in cs553x_init_one()
319 	iounmap(controller->mmio);  in cs553x_init_one()
321 	kfree(controller);  in cs553x_init_one()
345 	int err = -ENXIO;  in cs553x_init()
351 		return -ENXIO;  in cs553x_init()
357 		return -ENXIO;  in cs553x_init()
359 	/* If it doesn't have the NAND controller enabled, abort */  in cs553x_init()
362 		pr_info("CS553x NAND controller: Flash I/O not enabled in MSR_DIVIL_BALL_OPTS.\n");  in cs553x_init()
363 		return -ENXIO;  in cs553x_init()
378 			mtd_device_register(nand_to_mtd(&controllers[i]->chip),  in cs553x_init()
394 		struct cs553x_nand_controller *controller = controllers[i];  in cs553x_cleanup()  local
395 		struct nand_chip *this = &controller->chip;  in cs553x_cleanup()
406 		kfree(mtd->name);  in cs553x_cleanup()
410 		iounmap(controller->mmio);  in cs553x_cleanup()
413 		kfree(controller);  in cs553x_cleanup()
421 MODULE_DESCRIPTION("NAND controller driver for AMD CS5535/CS5536 companion chip");