Lines Matching +full:non +full:- +full:gateable
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2010-2015 Broadcom Corporation
17 #include <linux/dma-mapping.h>
227 /* Some SoCs have a gateable clock for the controller */
237 /* List of NAND hosts (one for each chip-select) */
240 /* EDU info, per-transaction */
261 /* in-memory cache of the FLASH_CACHE, used only for some commands */
267 const u8 *cs_offsets; /* within each chip-select */
278 /* for low-power standby/resume only */
298 /* use for low-power standby/resume only */
329 BRCMNAND_CS1_BASE, /* CS1 regs, if non-contiguous */
343 BRCMNAND_OOB_READ_10_BASE, /* offset 0x10, if non-contiguous */
345 BRCMNAND_OOB_WRITE_10_BASE, /* offset 0x10, if non-contiguous */
349 /* BRCMNAND v2.1-v2.2 */
379 /* BRCMNAND v3.3-v4.0 */
439 /* BRCMNAND v6.0 - v7.1 */
537 /* Per chip-select offsets for v7.1 */
546 /* Per chip-select offsets for pre v7.1, except CS0 on <= v5.0 */
555 /* Per chip-select offset for <= v5.0 on CS0 only */
565 * Bitfields for the CFG and CFG_EXT registers. Pre-v7.1 controllers only had
580 /* Only for pre-v7.1 (with no CFG_EXT register) */
642 return brcmnand_soc_read(ctrl->soc, offs); in nand_readreg()
643 return brcmnand_readl(ctrl->nand_base + offs); in nand_readreg()
650 brcmnand_soc_write(ctrl->soc, val, offs); in nand_writereg()
652 brcmnand_writel(val, ctrl->nand_base + offs); in nand_writereg()
665 ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff; in brcmnand_revision_init()
668 if (ctrl->nand_version < 0x0201) { in brcmnand_revision_init()
669 dev_err(ctrl->dev, "version %#x not supported\n", in brcmnand_revision_init()
670 ctrl->nand_version); in brcmnand_revision_init()
671 return -ENODEV; in brcmnand_revision_init()
675 if (ctrl->nand_version >= 0x0702) in brcmnand_revision_init()
676 ctrl->reg_offsets = brcmnand_regs_v72; in brcmnand_revision_init()
677 else if (ctrl->nand_version == 0x0701) in brcmnand_revision_init()
678 ctrl->reg_offsets = brcmnand_regs_v71; in brcmnand_revision_init()
679 else if (ctrl->nand_version >= 0x0600) in brcmnand_revision_init()
680 ctrl->reg_offsets = brcmnand_regs_v60; in brcmnand_revision_init()
681 else if (ctrl->nand_version >= 0x0500) in brcmnand_revision_init()
682 ctrl->reg_offsets = brcmnand_regs_v50; in brcmnand_revision_init()
683 else if (ctrl->nand_version >= 0x0303) in brcmnand_revision_init()
684 ctrl->reg_offsets = brcmnand_regs_v33; in brcmnand_revision_init()
685 else if (ctrl->nand_version >= 0x0201) in brcmnand_revision_init()
686 ctrl->reg_offsets = brcmnand_regs_v21; in brcmnand_revision_init()
688 /* Chip-select stride */ in brcmnand_revision_init()
689 if (ctrl->nand_version >= 0x0701) in brcmnand_revision_init()
690 ctrl->reg_spacing = 0x14; in brcmnand_revision_init()
692 ctrl->reg_spacing = 0x10; in brcmnand_revision_init()
694 /* Per chip-select registers */ in brcmnand_revision_init()
695 if (ctrl->nand_version >= 0x0701) { in brcmnand_revision_init()
696 ctrl->cs_offsets = brcmnand_cs_offsets_v71; in brcmnand_revision_init()
698 ctrl->cs_offsets = brcmnand_cs_offsets; in brcmnand_revision_init()
700 /* v3.3-5.0 have a different CS0 offset layout */ in brcmnand_revision_init()
701 if (ctrl->nand_version >= 0x0303 && in brcmnand_revision_init()
702 ctrl->nand_version <= 0x0500) in brcmnand_revision_init()
703 ctrl->cs0_offsets = brcmnand_cs_offsets_cs0; in brcmnand_revision_init()
707 if (ctrl->nand_version >= 0x0701) { in brcmnand_revision_init()
708 /* >= v7.1 use nice power-of-2 values! */ in brcmnand_revision_init()
709 ctrl->max_page_size = 16 * 1024; in brcmnand_revision_init()
710 ctrl->max_block_size = 2 * 1024 * 1024; in brcmnand_revision_init()
712 if (ctrl->nand_version >= 0x0304) in brcmnand_revision_init()
713 ctrl->page_sizes = page_sizes_v3_4; in brcmnand_revision_init()
714 else if (ctrl->nand_version >= 0x0202) in brcmnand_revision_init()
715 ctrl->page_sizes = page_sizes_v2_2; in brcmnand_revision_init()
717 ctrl->page_sizes = page_sizes_v2_1; in brcmnand_revision_init()
719 if (ctrl->nand_version >= 0x0202) in brcmnand_revision_init()
720 ctrl->page_size_shift = CFG_PAGE_SIZE_SHIFT; in brcmnand_revision_init()
722 ctrl->page_size_shift = CFG_PAGE_SIZE_SHIFT_v2_1; in brcmnand_revision_init()
724 if (ctrl->nand_version >= 0x0600) in brcmnand_revision_init()
725 ctrl->block_sizes = block_sizes_v6; in brcmnand_revision_init()
726 else if (ctrl->nand_version >= 0x0400) in brcmnand_revision_init()
727 ctrl->block_sizes = block_sizes_v4; in brcmnand_revision_init()
728 else if (ctrl->nand_version >= 0x0202) in brcmnand_revision_init()
729 ctrl->block_sizes = block_sizes_v2_2; in brcmnand_revision_init()
731 ctrl->block_sizes = block_sizes_v2_1; in brcmnand_revision_init()
733 if (ctrl->nand_version < 0x0400) { in brcmnand_revision_init()
734 if (ctrl->nand_version < 0x0202) in brcmnand_revision_init()
735 ctrl->max_page_size = 2048; in brcmnand_revision_init()
737 ctrl->max_page_size = 4096; in brcmnand_revision_init()
738 ctrl->max_block_size = 512 * 1024; in brcmnand_revision_init()
743 if (ctrl->nand_version == 0x0702) in brcmnand_revision_init()
744 ctrl->max_oob = 128; in brcmnand_revision_init()
745 else if (ctrl->nand_version >= 0x0600) in brcmnand_revision_init()
746 ctrl->max_oob = 64; in brcmnand_revision_init()
747 else if (ctrl->nand_version >= 0x0500) in brcmnand_revision_init()
748 ctrl->max_oob = 32; in brcmnand_revision_init()
750 ctrl->max_oob = 16; in brcmnand_revision_init()
753 if (ctrl->nand_version >= 0x0600 && ctrl->nand_version != 0x0601) in brcmnand_revision_init()
754 ctrl->features |= BRCMNAND_HAS_PREFETCH; in brcmnand_revision_init()
760 if (ctrl->nand_version >= 0x0700) in brcmnand_revision_init()
761 ctrl->features |= BRCMNAND_HAS_CACHE_MODE; in brcmnand_revision_init()
763 if (ctrl->nand_version >= 0x0500) in brcmnand_revision_init()
764 ctrl->features |= BRCMNAND_HAS_1K_SECTORS; in brcmnand_revision_init()
766 if (ctrl->nand_version >= 0x0700) in brcmnand_revision_init()
767 ctrl->features |= BRCMNAND_HAS_WP; in brcmnand_revision_init()
768 else if (of_property_read_bool(ctrl->dev->of_node, "brcm,nand-has-wp")) in brcmnand_revision_init()
769 ctrl->features |= BRCMNAND_HAS_WP; in brcmnand_revision_init()
772 if (ctrl->nand_version == 0x0702) in brcmnand_revision_init()
773 ctrl->ecc_level_shift = ACC_CONTROL_ECC_EXT_SHIFT; in brcmnand_revision_init()
775 ctrl->ecc_level_shift = ACC_CONTROL_ECC_SHIFT; in brcmnand_revision_init()
783 if (ctrl->nand_version >= 0x0703) in brcmnand_flash_dma_revision_init()
784 ctrl->flash_dma_offsets = flash_dma_regs_v4; in brcmnand_flash_dma_revision_init()
785 else if (ctrl->nand_version == 0x0602) in brcmnand_flash_dma_revision_init()
786 ctrl->flash_dma_offsets = flash_dma_regs_v0; in brcmnand_flash_dma_revision_init()
788 ctrl->flash_dma_offsets = flash_dma_regs_v1; in brcmnand_flash_dma_revision_init()
794 u16 offs = ctrl->reg_offsets[reg]; in brcmnand_read_reg()
805 u16 offs = ctrl->reg_offsets[reg]; in brcmnand_write_reg()
825 return brcmnand_soc_read(ctrl->soc, BRCMNAND_NON_MMIO_FC_ADDR); in brcmnand_read_fc()
826 return __raw_readl(ctrl->nand_fc + word * 4); in brcmnand_read_fc()
833 brcmnand_soc_write(ctrl->soc, val, BRCMNAND_NON_MMIO_FC_ADDR); in brcmnand_write_fc()
835 __raw_writel(val, ctrl->nand_fc + word * 4); in brcmnand_write_fc()
841 u16 offs = ctrl->edu_offsets[reg]; in edu_writel()
843 brcmnand_writel(val, ctrl->edu_base + offs); in edu_writel()
849 u16 offs = ctrl->edu_offsets[reg]; in edu_readl()
851 return brcmnand_readl(ctrl->edu_base + offs); in edu_readl()
857 struct brcmnand_soc *soc = ctrl->soc; in brcmnand_read_data_bus()
860 if (soc && soc->read_data_bus) { in brcmnand_read_data_bus()
861 soc->read_data_bus(soc, flash_cache, buffer, fc_words); in brcmnand_read_data_bus()
906 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_set_cmd_addr()
909 (host->cs << 16) | ((addr >> 32) & 0xffff)); in brcmnand_set_cmd_addr()
919 u16 offs_cs0 = ctrl->reg_offsets[BRCMNAND_CS0_BASE]; in brcmnand_cs_offset()
920 u16 offs_cs1 = ctrl->reg_offsets[BRCMNAND_CS1_BASE]; in brcmnand_cs_offset()
923 if (cs == 0 && ctrl->cs0_offsets) in brcmnand_cs_offset()
924 cs_offs = ctrl->cs0_offsets[reg]; in brcmnand_cs_offset()
926 cs_offs = ctrl->cs_offsets[reg]; in brcmnand_cs_offset()
929 return offs_cs1 + (cs - 1) * ctrl->reg_spacing + cs_offs; in brcmnand_cs_offset()
931 return offs_cs0 + cs * ctrl->reg_spacing + cs_offs; in brcmnand_cs_offset()
936 if (ctrl->nand_version < 0x0600) in brcmnand_count_corrected()
943 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_wr_corr_thresh()
946 int cs = host->cs; in brcmnand_wr_corr_thresh()
948 if (!ctrl->reg_offsets[reg]) in brcmnand_wr_corr_thresh()
951 if (ctrl->nand_version == 0x0702) in brcmnand_wr_corr_thresh()
953 else if (ctrl->nand_version >= 0x0600) in brcmnand_wr_corr_thresh()
955 else if (ctrl->nand_version >= 0x0500) in brcmnand_wr_corr_thresh()
960 if (ctrl->nand_version >= 0x0702) { in brcmnand_wr_corr_thresh()
964 } else if (ctrl->nand_version >= 0x0600) { in brcmnand_wr_corr_thresh()
969 brcmnand_rmw_reg(ctrl, reg, (bits - 1) << shift, shift, val); in brcmnand_wr_corr_thresh()
974 /* Kludge for the BCMA-based NAND controller which does not actually in brcmnand_cmd_shift()
977 if (ctrl->nand_version == 0x0304 && brcmnand_non_mmio_ops(ctrl)) in brcmnand_cmd_shift()
980 if (ctrl->nand_version < 0x0602) in brcmnand_cmd_shift()
987 if (ctrl->nand_version == 0x0702) in brcmnand_spare_area_mask()
989 else if (ctrl->nand_version >= 0x0600) in brcmnand_spare_area_mask()
991 else if (ctrl->nand_version >= 0x0303) in brcmnand_spare_area_mask()
999 u32 mask = (ctrl->nand_version >= 0x0600) ? 0x1f : 0x0f; in brcmnand_ecc_level_mask()
1004 if (ctrl->nand_version == 0x0702) in brcmnand_ecc_level_mask()
1012 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_set_ecc_enabled()
1013 u16 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL); in brcmnand_set_ecc_enabled()
1020 acc_control |= host->hwcfg.ecc_level << ctrl->ecc_level_shift; in brcmnand_set_ecc_enabled()
1031 if (ctrl->nand_version >= 0x0702) in brcmnand_sector_1k_shift()
1033 else if (ctrl->nand_version >= 0x0600) in brcmnand_sector_1k_shift()
1035 else if (ctrl->nand_version >= 0x0500) in brcmnand_sector_1k_shift()
1038 return -1; in brcmnand_sector_1k_shift()
1043 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_get_sector_size_1k()
1045 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_get_sector_size_1k()
1059 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_set_sector_size_1k()
1061 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_set_sector_size_1k()
1076 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_get_spare_size()
1077 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_get_spare_size()
1086 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_get_ecc_settings()
1087 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_get_ecc_settings()
1095 ecc_level = (acc & brcmnand_ecc_level_mask(ctrl)) >> ctrl->ecc_level_shift; in brcmnand_get_ecc_settings()
1097 chip->ecc.strength = ecc_level * 2; in brcmnand_get_ecc_settings()
1099 chip->ecc.strength = 1; /* hamming */ in brcmnand_get_ecc_settings()
1101 chip->ecc.strength = ecc_level; in brcmnand_get_ecc_settings()
1103 if (chip->ecc.size == 0) { in brcmnand_get_ecc_settings()
1105 chip->ecc.size = 1024; in brcmnand_get_ecc_settings()
1107 chip->ecc.size = 512; in brcmnand_get_ecc_settings()
1124 struct brcmnand_controller *ctrl = host->ctrl; in bcmnand_ctrl_poll_status()
1154 dev_err(ctrl->dev, "timeout on status poll (expected %x got %x)\n", in bcmnand_ctrl_poll_status()
1157 return -ETIMEDOUT; in bcmnand_ctrl_poll_status()
1173 return ctrl->flash_dma_base; in has_flash_dma()
1178 return ctrl->edu_base; in has_edu()
1188 if (ctrl->pio_poll_mode) in disable_ctrl_irqs()
1192 ctrl->flash_dma_base = NULL; in disable_ctrl_irqs()
1193 disable_irq(ctrl->dma_irq); in disable_ctrl_irqs()
1196 disable_irq(ctrl->irq); in disable_ctrl_irqs()
1197 ctrl->pio_poll_mode = true; in disable_ctrl_irqs()
1209 u16 offs = ctrl->flash_dma_offsets[dma_reg]; in flash_dma_writel()
1211 brcmnand_writel(val, ctrl->flash_dma_base + offs); in flash_dma_writel()
1217 u16 offs = ctrl->flash_dma_offsets[dma_reg]; in flash_dma_readl()
1219 return brcmnand_readl(ctrl->flash_dma_base + offs); in flash_dma_readl()
1222 /* Low-level operation types: command, address, write, or read */
1237 if (ctrl->nand_version <= 0x0701) in is_hamming_ecc()
1238 return cfg->sector_size_1k == 0 && cfg->spare_area_size == 16 && in is_hamming_ecc()
1239 cfg->ecc_level == 15; in is_hamming_ecc()
1241 return cfg->sector_size_1k == 0 && ((cfg->spare_area_size == 16 && in is_hamming_ecc()
1242 cfg->ecc_level == 15) || in is_hamming_ecc()
1243 (cfg->spare_area_size == 28 && cfg->ecc_level == 16)); in is_hamming_ecc()
1247 * Set mtd->ooblayout to the appropriate mtd_ooblayout_ops given
1249 * Returns -ERRCODE on failure.
1256 struct brcmnand_cfg *cfg = &host->hwcfg; in brcmnand_hamming_ooblayout_ecc()
1257 int sas = cfg->spare_area_size << cfg->sector_size_1k; in brcmnand_hamming_ooblayout_ecc()
1258 int sectors = cfg->page_size / (512 << cfg->sector_size_1k); in brcmnand_hamming_ooblayout_ecc()
1261 return -ERANGE; in brcmnand_hamming_ooblayout_ecc()
1263 oobregion->offset = (section * sas) + 6; in brcmnand_hamming_ooblayout_ecc()
1264 oobregion->length = 3; in brcmnand_hamming_ooblayout_ecc()
1274 struct brcmnand_cfg *cfg = &host->hwcfg; in brcmnand_hamming_ooblayout_free()
1275 int sas = cfg->spare_area_size << cfg->sector_size_1k; in brcmnand_hamming_ooblayout_free()
1276 int sectors = cfg->page_size / (512 << cfg->sector_size_1k); in brcmnand_hamming_ooblayout_free()
1280 return -ERANGE; in brcmnand_hamming_ooblayout_free()
1287 oobregion->offset = ((section - 1) * sas) + 9; in brcmnand_hamming_ooblayout_free()
1289 if (cfg->page_size > 512) { in brcmnand_hamming_ooblayout_free()
1291 oobregion->offset = 2; in brcmnand_hamming_ooblayout_free()
1294 oobregion->offset = 0; in brcmnand_hamming_ooblayout_free()
1295 next--; in brcmnand_hamming_ooblayout_free()
1299 oobregion->length = next - oobregion->offset; in brcmnand_hamming_ooblayout_free()
1314 struct brcmnand_cfg *cfg = &host->hwcfg; in brcmnand_bch_ooblayout_ecc()
1315 int sas = cfg->spare_area_size << cfg->sector_size_1k; in brcmnand_bch_ooblayout_ecc()
1316 int sectors = cfg->page_size / (512 << cfg->sector_size_1k); in brcmnand_bch_ooblayout_ecc()
1319 return -ERANGE; in brcmnand_bch_ooblayout_ecc()
1321 oobregion->offset = ((section + 1) * sas) - chip->ecc.bytes; in brcmnand_bch_ooblayout_ecc()
1322 oobregion->length = chip->ecc.bytes; in brcmnand_bch_ooblayout_ecc()
1332 struct brcmnand_cfg *cfg = &host->hwcfg; in brcmnand_bch_ooblayout_free_lp()
1333 int sas = cfg->spare_area_size << cfg->sector_size_1k; in brcmnand_bch_ooblayout_free_lp()
1334 int sectors = cfg->page_size / (512 << cfg->sector_size_1k); in brcmnand_bch_ooblayout_free_lp()
1337 return -ERANGE; in brcmnand_bch_ooblayout_free_lp()
1339 if (sas <= chip->ecc.bytes) in brcmnand_bch_ooblayout_free_lp()
1342 oobregion->offset = section * sas; in brcmnand_bch_ooblayout_free_lp()
1343 oobregion->length = sas - chip->ecc.bytes; in brcmnand_bch_ooblayout_free_lp()
1346 oobregion->offset++; in brcmnand_bch_ooblayout_free_lp()
1347 oobregion->length--; in brcmnand_bch_ooblayout_free_lp()
1358 struct brcmnand_cfg *cfg = &host->hwcfg; in brcmnand_bch_ooblayout_free_sp()
1359 int sas = cfg->spare_area_size << cfg->sector_size_1k; in brcmnand_bch_ooblayout_free_sp()
1361 if (section > 1 || sas - chip->ecc.bytes < 6 || in brcmnand_bch_ooblayout_free_sp()
1362 (section && sas - chip->ecc.bytes == 6)) in brcmnand_bch_ooblayout_free_sp()
1363 return -ERANGE; in brcmnand_bch_ooblayout_free_sp()
1366 oobregion->offset = 0; in brcmnand_bch_ooblayout_free_sp()
1367 oobregion->length = 5; in brcmnand_bch_ooblayout_free_sp()
1369 oobregion->offset = 6; in brcmnand_bch_ooblayout_free_sp()
1370 oobregion->length = sas - chip->ecc.bytes - 6; in brcmnand_bch_ooblayout_free_sp()
1388 struct brcmnand_cfg *p = &host->hwcfg; in brcmstb_choose_ecc_layout()
1389 struct mtd_info *mtd = nand_to_mtd(&host->chip); in brcmstb_choose_ecc_layout()
1390 struct nand_ecc_ctrl *ecc = &host->chip.ecc; in brcmstb_choose_ecc_layout()
1391 unsigned int ecc_level = p->ecc_level; in brcmstb_choose_ecc_layout()
1392 int sas = p->spare_area_size << p->sector_size_1k; in brcmstb_choose_ecc_layout()
1393 int sectors = p->page_size / (512 << p->sector_size_1k); in brcmstb_choose_ecc_layout()
1395 if (p->sector_size_1k) in brcmstb_choose_ecc_layout()
1398 if (is_hamming_ecc(host->ctrl, p)) { in brcmstb_choose_ecc_layout()
1399 ecc->bytes = 3 * sectors; in brcmstb_choose_ecc_layout()
1410 ecc->bytes = DIV_ROUND_UP(ecc_level * 14, 8); in brcmstb_choose_ecc_layout()
1411 if (p->page_size == 512) in brcmstb_choose_ecc_layout()
1416 if (ecc->bytes >= sas) { in brcmstb_choose_ecc_layout()
1417 dev_err(&host->pdev->dev, in brcmstb_choose_ecc_layout()
1419 ecc->bytes, sas); in brcmstb_choose_ecc_layout()
1420 return -EINVAL; in brcmstb_choose_ecc_layout()
1430 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_wp()
1432 if ((ctrl->features & BRCMNAND_HAS_WP) && wp_on == 1) { in brcmnand_wp()
1433 static int old_wp = -1; in brcmnand_wp()
1437 dev_dbg(ctrl->dev, "WP %s\n", wp ? "on" : "off"); in brcmnand_wp()
1465 dev_err_ratelimited(&host->pdev->dev, in brcmnand_wp()
1476 offset0 = ctrl->reg_offsets[BRCMNAND_OOB_READ_BASE]; in oob_reg_read()
1477 offset10 = ctrl->reg_offsets[BRCMNAND_OOB_READ_10_BASE]; in oob_reg_read()
1479 if (offs >= ctrl->max_oob) in oob_reg_read()
1483 reg_offs = offset10 + ((offs - 0x10) & ~0x03); in oob_reg_read()
1487 return nand_readreg(ctrl, reg_offs) >> (24 - ((offs & 0x03) << 3)); in oob_reg_read()
1495 offset0 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_BASE]; in oob_reg_write()
1496 offset10 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_10_BASE]; in oob_reg_write()
1498 if (offs >= ctrl->max_oob) in oob_reg_write()
1502 reg_offs = offset10 + ((offs - 0x10) & ~0x03); in oob_reg_write()
1510 * read_oob_from_regs - read data from OOB registers
1512 * @i: sub-page sector index
1525 tbytes = max(0, tbytes - (int)ctrl->max_oob); in read_oob_from_regs()
1526 tbytes = min_t(int, tbytes, ctrl->max_oob); in read_oob_from_regs()
1534 * write_oob_to_regs - write data to OOB registers
1535 * @i: sub-page sector index
1550 tbytes = max(0, tbytes - (int)ctrl->max_oob); in write_oob_to_regs()
1551 tbytes = min_t(int, tbytes, ctrl->max_oob); in write_oob_to_regs()
1591 if (ctrl->edu_count) { in brcmnand_edu_irq()
1592 ctrl->edu_count--; in brcmnand_edu_irq()
1599 if (ctrl->edu_count) { in brcmnand_edu_irq()
1600 ctrl->edu_dram_addr += FC_BYTES; in brcmnand_edu_irq()
1601 ctrl->edu_ext_addr += FC_BYTES; in brcmnand_edu_irq()
1603 edu_writel(ctrl, EDU_DRAM_ADDR, (u32)ctrl->edu_dram_addr); in brcmnand_edu_irq()
1605 edu_writel(ctrl, EDU_EXT_ADDR, ctrl->edu_ext_addr); in brcmnand_edu_irq()
1608 if (ctrl->oob) { in brcmnand_edu_irq()
1609 if (ctrl->edu_cmd == EDU_CMD_READ) { in brcmnand_edu_irq()
1610 ctrl->oob += read_oob_from_regs(ctrl, in brcmnand_edu_irq()
1611 ctrl->edu_count + 1, in brcmnand_edu_irq()
1612 ctrl->oob, ctrl->sas, in brcmnand_edu_irq()
1613 ctrl->sector_size_1k); in brcmnand_edu_irq()
1616 ctrl->edu_ext_addr); in brcmnand_edu_irq()
1618 ctrl->oob += write_oob_to_regs(ctrl, in brcmnand_edu_irq()
1619 ctrl->edu_count, in brcmnand_edu_irq()
1620 ctrl->oob, ctrl->sas, in brcmnand_edu_irq()
1621 ctrl->sector_size_1k); in brcmnand_edu_irq()
1626 edu_writel(ctrl, EDU_CMD, ctrl->edu_cmd); in brcmnand_edu_irq()
1632 complete(&ctrl->edu_done); in brcmnand_edu_irq()
1642 if (ctrl->dma_pending) in brcmnand_ctlrdy_irq()
1646 if (ctrl->edu_pending) { in brcmnand_ctlrdy_irq()
1647 if (irq == ctrl->irq && ((int)ctrl->edu_irq >= 0)) in brcmnand_ctlrdy_irq()
1655 complete(&ctrl->done); in brcmnand_ctlrdy_irq()
1659 /* Handle SoC-specific interrupt hardware */
1664 if (ctrl->soc->ctlrdy_ack(ctrl->soc)) in brcmnand_irq()
1674 complete(&ctrl->dma_done); in brcmnand_dma_irq()
1681 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_send_cmd()
1687 dev_dbg(ctrl->dev, "send native cmd %d addr 0x%llx\n", cmd, cmd_addr); in brcmnand_send_cmd()
1695 if (ctrl->cmd_pending && in brcmnand_send_cmd()
1699 BUG_ON(ctrl->cmd_pending != 0); in brcmnand_send_cmd()
1700 ctrl->cmd_pending = cmd; in brcmnand_send_cmd()
1713 struct brcmnand_controller *ctrl = host->ctrl; in brcmstb_nand_wait_for_completion()
1718 if (mtd->oops_panic_write || ctrl->irq < 0) { in brcmstb_nand_wait_for_completion()
1728 sts = wait_for_completion_timeout(&ctrl->done, timeo); in brcmstb_nand_wait_for_completion()
1738 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_waitfunc()
1741 dev_dbg(ctrl->dev, "wait on native cmd %d\n", ctrl->cmd_pending); in brcmnand_waitfunc()
1742 if (ctrl->cmd_pending) in brcmnand_waitfunc()
1745 ctrl->cmd_pending = 0; in brcmnand_waitfunc()
1750 dev_err_ratelimited(ctrl->dev, in brcmnand_waitfunc()
1752 dev_err_ratelimited(ctrl->dev, "intfc status %08x\n", in brcmnand_waitfunc()
1754 return -ETIMEDOUT; in brcmnand_waitfunc()
1762 struct nand_chip *chip = &host->chip; in brcmnand_status()
1773 struct nand_chip *chip = &host->chip; in brcmnand_reset()
1794 struct nand_chip *chip = &host->chip; in brcmnand_low_level_op()
1795 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_low_level_op()
1820 dev_dbg(ctrl->dev, "ll_op cmd %#x\n", tmp); in brcmnand_low_level_op()
1835 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_edu_trans()
1836 struct brcmnand_cfg *cfg = &host->hwcfg; in brcmnand_edu_trans()
1844 dev_dbg(ctrl->dev, "EDU %s %p:%p\n", ((edu_cmd == EDU_CMD_READ) ? in brcmnand_edu_trans()
1847 pa = dma_map_single(ctrl->dev, buf, len, dir); in brcmnand_edu_trans()
1848 if (dma_mapping_error(ctrl->dev, pa)) { in brcmnand_edu_trans()
1849 dev_err(ctrl->dev, "unable to map buffer for EDU DMA\n"); in brcmnand_edu_trans()
1850 return -ENOMEM; in brcmnand_edu_trans()
1853 ctrl->edu_pending = true; in brcmnand_edu_trans()
1854 ctrl->edu_dram_addr = pa; in brcmnand_edu_trans()
1855 ctrl->edu_ext_addr = addr; in brcmnand_edu_trans()
1856 ctrl->edu_cmd = edu_cmd; in brcmnand_edu_trans()
1857 ctrl->edu_count = trans; in brcmnand_edu_trans()
1858 ctrl->sas = cfg->spare_area_size; in brcmnand_edu_trans()
1859 ctrl->oob = oob; in brcmnand_edu_trans()
1861 edu_writel(ctrl, EDU_DRAM_ADDR, (u32)ctrl->edu_dram_addr); in brcmnand_edu_trans()
1863 edu_writel(ctrl, EDU_EXT_ADDR, ctrl->edu_ext_addr); in brcmnand_edu_trans()
1868 if (ctrl->oob && (ctrl->edu_cmd == EDU_CMD_WRITE)) { in brcmnand_edu_trans()
1870 ctrl->edu_ext_addr); in brcmnand_edu_trans()
1872 ctrl->oob += write_oob_to_regs(ctrl, in brcmnand_edu_trans()
1874 ctrl->oob, ctrl->sas, in brcmnand_edu_trans()
1875 ctrl->sector_size_1k); in brcmnand_edu_trans()
1880 edu_writel(ctrl, EDU_CMD, ctrl->edu_cmd); in brcmnand_edu_trans()
1883 if (wait_for_completion_timeout(&ctrl->edu_done, timeo) <= 0) { in brcmnand_edu_trans()
1884 dev_err(ctrl->dev, in brcmnand_edu_trans()
1890 dma_unmap_single(ctrl->dev, pa, len, dir); in brcmnand_edu_trans()
1893 if (ctrl->oob && (ctrl->edu_cmd == EDU_CMD_READ)) { in brcmnand_edu_trans()
1894 ctrl->oob += read_oob_from_regs(ctrl, in brcmnand_edu_trans()
1896 ctrl->oob, ctrl->sas, in brcmnand_edu_trans()
1897 ctrl->sector_size_1k); in brcmnand_edu_trans()
1904 dev_info(ctrl->dev, "program failed at %llx\n", in brcmnand_edu_trans()
1906 ret = -EIO; in brcmnand_edu_trans()
1911 dev_warn(ctrl->dev, "EDU still active: %#x\n", in brcmnand_edu_trans()
1915 dev_warn(ctrl->dev, "EDU RBUS error at addr %llx\n", in brcmnand_edu_trans()
1917 ret = -EIO; in brcmnand_edu_trans()
1920 ctrl->edu_pending = false; in brcmnand_edu_trans()
1936 ret = -EUCLEAN; in brcmnand_edu_trans()
1938 ret = -EBADMSG; in brcmnand_edu_trans()
1947 * - Is this descriptor the beginning or end of a linked list?
1948 * - What is the (DMA) address of the next descriptor in the linked list?
1958 desc->next_desc = lower_32_bits(next_desc); in brcmnand_fill_dma_desc()
1959 desc->next_desc_ext = upper_32_bits(next_desc); in brcmnand_fill_dma_desc()
1960 desc->cmd_irq = (dma_cmd << 24) | in brcmnand_fill_dma_desc()
1964 desc->cmd_irq |= 0x01 << 12; in brcmnand_fill_dma_desc()
1966 desc->dram_addr = lower_32_bits(buf); in brcmnand_fill_dma_desc()
1967 desc->dram_addr_ext = upper_32_bits(buf); in brcmnand_fill_dma_desc()
1968 desc->tfr_len = len; in brcmnand_fill_dma_desc()
1969 desc->total_len = len; in brcmnand_fill_dma_desc()
1970 desc->flash_addr = lower_32_bits(addr); in brcmnand_fill_dma_desc()
1971 desc->flash_addr_ext = upper_32_bits(addr); in brcmnand_fill_dma_desc()
1972 desc->cs = host->cs; in brcmnand_fill_dma_desc()
1973 desc->status_valid = 0x01; in brcmnand_fill_dma_desc()
1982 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_dma_run()
1987 if (ctrl->nand_version > 0x0602) { in brcmnand_dma_run()
1994 ctrl->dma_pending = true; in brcmnand_dma_run()
1998 if (wait_for_completion_timeout(&ctrl->dma_done, timeo) <= 0) { in brcmnand_dma_run()
1999 dev_err(ctrl->dev, in brcmnand_dma_run()
2004 ctrl->dma_pending = false; in brcmnand_dma_run()
2011 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_dma_trans()
2015 buf_pa = dma_map_single(ctrl->dev, buf, len, dir); in brcmnand_dma_trans()
2016 if (dma_mapping_error(ctrl->dev, buf_pa)) { in brcmnand_dma_trans()
2017 dev_err(ctrl->dev, "unable to map buffer for DMA\n"); in brcmnand_dma_trans()
2018 return -ENOMEM; in brcmnand_dma_trans()
2021 brcmnand_fill_dma_desc(host, ctrl->dma_desc, addr, buf_pa, len, in brcmnand_dma_trans()
2024 brcmnand_dma_run(host, ctrl->dma_pa); in brcmnand_dma_trans()
2026 dma_unmap_single(ctrl->dev, buf_pa, len, dir); in brcmnand_dma_trans()
2028 if (ctrl->dma_desc->status_valid & FLASH_DMA_ECC_ERROR) in brcmnand_dma_trans()
2029 return -EBADMSG; in brcmnand_dma_trans()
2030 else if (ctrl->dma_desc->status_valid & FLASH_DMA_CORR_ERROR) in brcmnand_dma_trans()
2031 return -EUCLEAN; in brcmnand_dma_trans()
2044 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_read_by_pio()
2056 brcmnand_soc_data_bus_prepare(ctrl->soc, false); in brcmnand_read_by_pio()
2058 brcmnand_read_data_bus(ctrl, ctrl->nand_fc, buf, FC_WORDS); in brcmnand_read_by_pio()
2061 brcmnand_soc_data_bus_unprepare(ctrl->soc, false); in brcmnand_read_by_pio()
2066 mtd->oobsize / trans, in brcmnand_read_by_pio()
2067 host->hwcfg.sector_size_1k); in brcmnand_read_by_pio()
2069 if (ret != -EBADMSG) { in brcmnand_read_by_pio()
2073 ret = -EBADMSG; in brcmnand_read_by_pio()
2080 ret = -EUCLEAN; in brcmnand_read_by_pio()
2095 * On a real error, return a negative error code (-EBADMSG for ECC error), and
2098 * bitflips-per-ECC-sector to the caller.
2107 int page = addr >> chip->page_shift; in brcmstb_nand_verify_erased_page()
2116 ret = chip->ecc.read_page_raw(chip, buf, true, page); in brcmstb_nand_verify_erased_page()
2120 for (i = 0; i < chip->ecc.steps; i++) { in brcmstb_nand_verify_erased_page()
2121 ecc_chunk = buf + chip->ecc.size * i; in brcmstb_nand_verify_erased_page()
2124 ecc_bytes = chip->oob_poi + ecc.offset; in brcmstb_nand_verify_erased_page()
2126 ret = nand_check_erased_ecc_chunk(ecc_chunk, chip->ecc.size, in brcmstb_nand_verify_erased_page()
2129 chip->ecc.strength); in brcmstb_nand_verify_erased_page()
2143 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_read()
2149 dev_dbg(ctrl->dev, "read %llx -> %p\n", (unsigned long long)addr, buf); in brcmnand_read()
2154 if (ctrl->dma_trans && (has_edu(ctrl) || !oob) && in brcmnand_read()
2156 err = ctrl->dma_trans(host, addr, buf, oob, in brcmnand_read()
2164 return -EIO; in brcmnand_read()
2172 memset(oob, 0x99, mtd->oobsize); in brcmnand_read()
2187 if ((ctrl->nand_version == 0x0700) || in brcmnand_read()
2188 (ctrl->nand_version == 0x0701)) { in brcmnand_read()
2199 if (ctrl->nand_version < 0x0702) { in brcmnand_read()
2207 dev_err(ctrl->dev, "uncorrectable error at 0x%llx\n", in brcmnand_read()
2209 mtd->ecc_stats.failed++; in brcmnand_read()
2222 dev_dbg(ctrl->dev, "corrected error at 0x%llx\n", in brcmnand_read()
2224 mtd->ecc_stats.corrected += corrected; in brcmnand_read()
2225 /* Always exceed the software-imposed threshold */ in brcmnand_read()
2226 return max(mtd->bitflip_threshold, corrected); in brcmnand_read()
2237 u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL; in brcmnand_read_page()
2238 u64 addr = (u64)page << chip->page_shift; in brcmnand_read_page()
2240 host->last_addr = addr; in brcmnand_read_page()
2242 return brcmnand_read(mtd, chip, host->last_addr, in brcmnand_read_page()
2243 mtd->writesize >> FC_SHIFT, (u32 *)buf, oob); in brcmnand_read_page()
2251 u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL; in brcmnand_read_page_raw()
2253 u64 addr = (u64)page << chip->page_shift; in brcmnand_read_page_raw()
2255 host->last_addr = addr; in brcmnand_read_page_raw()
2258 ret = brcmnand_read(mtd, chip, host->last_addr, in brcmnand_read_page_raw()
2259 mtd->writesize >> FC_SHIFT, (u32 *)buf, oob); in brcmnand_read_page_raw()
2268 return brcmnand_read(mtd, chip, (u64)page << chip->page_shift, in brcmnand_read_oob()
2269 mtd->writesize >> FC_SHIFT, in brcmnand_read_oob()
2270 NULL, (u8 *)chip->oob_poi); in brcmnand_read_oob()
2279 brcmnand_read(mtd, chip, (u64)page << chip->page_shift, in brcmnand_read_oob_raw()
2280 mtd->writesize >> FC_SHIFT, in brcmnand_read_oob_raw()
2281 NULL, (u8 *)chip->oob_poi); in brcmnand_read_oob_raw()
2290 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_write()
2291 unsigned int i, j, trans = mtd->writesize >> FC_SHIFT; in brcmnand_write()
2294 dev_dbg(ctrl->dev, "write %llx <- %p\n", (unsigned long long)addr, buf); in brcmnand_write()
2297 dev_warn(ctrl->dev, "unaligned buffer: %p\n", buf); in brcmnand_write()
2303 for (i = 0; i < ctrl->max_oob; i += 4) in brcmnand_write()
2306 if (mtd->oops_panic_write) in brcmnand_write()
2311 if (ctrl->dma_trans(host, addr, (u32 *)buf, oob, mtd->writesize, in brcmnand_write()
2314 ret = -EIO; in brcmnand_write()
2324 brcmnand_soc_data_bus_prepare(ctrl->soc, false); in brcmnand_write()
2329 brcmnand_soc_data_bus_unprepare(ctrl->soc, false); in brcmnand_write()
2337 mtd->oobsize / trans, in brcmnand_write()
2338 host->hwcfg.sector_size_1k); in brcmnand_write()
2346 dev_info(ctrl->dev, "program failed at %llx\n", in brcmnand_write()
2348 ret = -EIO; in brcmnand_write()
2362 void *oob = oob_required ? chip->oob_poi : NULL; in brcmnand_write_page()
2363 u64 addr = (u64)page << chip->page_shift; in brcmnand_write_page()
2365 host->last_addr = addr; in brcmnand_write_page()
2367 return brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob); in brcmnand_write_page()
2375 void *oob = oob_required ? chip->oob_poi : NULL; in brcmnand_write_page_raw()
2376 u64 addr = (u64)page << chip->page_shift; in brcmnand_write_page_raw()
2379 host->last_addr = addr; in brcmnand_write_page_raw()
2381 ret = brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob); in brcmnand_write_page_raw()
2390 (u64)page << chip->page_shift, NULL, in brcmnand_write_oob()
2391 chip->oob_poi); in brcmnand_write_oob()
2401 ret = brcmnand_write(mtd, chip, (u64)page << chip->page_shift, NULL, in brcmnand_write_oob_raw()
2402 (u8 *)chip->oob_poi); in brcmnand_write_oob_raw()
2411 const struct nand_op_instr *instr = &op->instrs[i]; in brcmnand_exec_instr()
2412 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_exec_instr()
2422 last_op = ((i == (op->ninstrs - 1)) && (instr->type != NAND_OP_WAITRDY_INSTR)) || in brcmnand_exec_instr()
2423 ((i == (op->ninstrs - 2)) && (op->instrs[i + 1].type == NAND_OP_WAITRDY_INSTR)); in brcmnand_exec_instr()
2425 switch (instr->type) { in brcmnand_exec_instr()
2427 brcmnand_low_level_op(host, LL_OP_CMD, instr->ctx.cmd.opcode, last_op); in brcmnand_exec_instr()
2431 for (i = 0; i < instr->ctx.addr.naddrs; i++) in brcmnand_exec_instr()
2432 brcmnand_low_level_op(host, LL_OP_ADDR, instr->ctx.addr.addrs[i], in brcmnand_exec_instr()
2433 last_op && (i == (instr->ctx.addr.naddrs - 1))); in brcmnand_exec_instr()
2437 in = instr->ctx.data.buf.in; in brcmnand_exec_instr()
2438 for (i = 0; i < instr->ctx.data.len; i++) { in brcmnand_exec_instr()
2440 last_op && (i == (instr->ctx.data.len - 1))); in brcmnand_exec_instr()
2441 in[i] = brcmnand_read_reg(host->ctrl, BRCMNAND_LL_RDATA); in brcmnand_exec_instr()
2446 out = instr->ctx.data.buf.out; in brcmnand_exec_instr()
2447 for (i = 0; i < instr->ctx.data.len; i++) in brcmnand_exec_instr()
2449 last_op && (i == (instr->ctx.data.len - 1))); in brcmnand_exec_instr()
2457 dev_err(ctrl->dev, "unsupported instruction type: %d\n", in brcmnand_exec_instr()
2458 instr->type); in brcmnand_exec_instr()
2459 ret = -EINVAL; in brcmnand_exec_instr()
2468 if (op->ninstrs == 2 && in brcmnand_op_is_status()
2469 op->instrs[0].type == NAND_OP_CMD_INSTR && in brcmnand_op_is_status()
2470 op->instrs[0].ctx.cmd.opcode == NAND_CMD_STATUS && in brcmnand_op_is_status()
2471 op->instrs[1].type == NAND_OP_DATA_IN_INSTR) in brcmnand_op_is_status()
2479 if (op->ninstrs == 2 && in brcmnand_op_is_reset()
2480 op->instrs[0].type == NAND_OP_CMD_INSTR && in brcmnand_op_is_reset()
2481 op->instrs[0].ctx.cmd.opcode == NAND_CMD_RESET && in brcmnand_op_is_reset()
2482 op->instrs[1].type == NAND_OP_WAITRDY_INSTR) in brcmnand_op_is_reset()
2502 status = op->instrs[1].ctx.data.buf.in; in brcmnand_exec_op()
2520 if (op->deassert_wp) in brcmnand_exec_op()
2523 for (i = 0; i < op->ninstrs; i++) { in brcmnand_exec_op()
2529 if (op->deassert_wp) in brcmnand_exec_op()
2536 * Per-CS setup (1 NAND device)
2542 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_set_cfg()
2543 struct nand_chip *chip = &host->chip; in brcmnand_set_cfg()
2544 u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG); in brcmnand_set_cfg()
2545 u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_set_cfg()
2547 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_set_cfg()
2552 if (ctrl->block_sizes) { in brcmnand_set_cfg()
2555 for (i = 0, found = 0; ctrl->block_sizes[i]; i++) in brcmnand_set_cfg()
2556 if (ctrl->block_sizes[i] * 1024 == cfg->block_size) { in brcmnand_set_cfg()
2561 dev_warn(ctrl->dev, "invalid block size %u\n", in brcmnand_set_cfg()
2562 cfg->block_size); in brcmnand_set_cfg()
2563 return -EINVAL; in brcmnand_set_cfg()
2566 block_size = ffs(cfg->block_size) - ffs(BRCMNAND_MIN_BLOCKSIZE); in brcmnand_set_cfg()
2569 if (cfg->block_size < BRCMNAND_MIN_BLOCKSIZE || (ctrl->max_block_size && in brcmnand_set_cfg()
2570 cfg->block_size > ctrl->max_block_size)) { in brcmnand_set_cfg()
2571 dev_warn(ctrl->dev, "invalid block size %u\n", in brcmnand_set_cfg()
2572 cfg->block_size); in brcmnand_set_cfg()
2576 if (ctrl->page_sizes) { in brcmnand_set_cfg()
2579 for (i = 0, found = 0; ctrl->page_sizes[i]; i++) in brcmnand_set_cfg()
2580 if (ctrl->page_sizes[i] == cfg->page_size) { in brcmnand_set_cfg()
2585 dev_warn(ctrl->dev, "invalid page size %u\n", in brcmnand_set_cfg()
2586 cfg->page_size); in brcmnand_set_cfg()
2587 return -EINVAL; in brcmnand_set_cfg()
2590 page_size = ffs(cfg->page_size) - ffs(BRCMNAND_MIN_PAGESIZE); in brcmnand_set_cfg()
2593 if (cfg->page_size < BRCMNAND_MIN_PAGESIZE || (ctrl->max_page_size && in brcmnand_set_cfg()
2594 cfg->page_size > ctrl->max_page_size)) { in brcmnand_set_cfg()
2595 dev_warn(ctrl->dev, "invalid page size %u\n", cfg->page_size); in brcmnand_set_cfg()
2596 return -EINVAL; in brcmnand_set_cfg()
2599 if (fls64(cfg->device_size) < fls64(BRCMNAND_MIN_DEVSIZE)) { in brcmnand_set_cfg()
2600 dev_warn(ctrl->dev, "invalid device size 0x%llx\n", in brcmnand_set_cfg()
2601 (unsigned long long)cfg->device_size); in brcmnand_set_cfg()
2602 return -EINVAL; in brcmnand_set_cfg()
2604 device_size = fls64(cfg->device_size) - fls64(BRCMNAND_MIN_DEVSIZE); in brcmnand_set_cfg()
2606 tmp = (cfg->blk_adr_bytes << CFG_BLK_ADR_BYTES_SHIFT) | in brcmnand_set_cfg()
2607 (cfg->col_adr_bytes << CFG_COL_ADR_BYTES_SHIFT) | in brcmnand_set_cfg()
2608 (cfg->ful_adr_bytes << CFG_FUL_ADR_BYTES_SHIFT) | in brcmnand_set_cfg()
2609 (!!(cfg->device_width == 16) << CFG_BUS_WIDTH_SHIFT) | in brcmnand_set_cfg()
2612 tmp |= (page_size << ctrl->page_size_shift) | in brcmnand_set_cfg()
2625 if (ctrl->nand_version >= 0x0302) { in brcmnand_set_cfg()
2626 tmp |= cfg->ecc_level << ctrl->ecc_level_shift; in brcmnand_set_cfg()
2627 tmp |= cfg->spare_area_size; in brcmnand_set_cfg()
2631 brcmnand_set_sector_size_1k(host, cfg->sector_size_1k); in brcmnand_set_cfg()
2633 /* threshold = ceil(BCH-level * 0.75) */ in brcmnand_set_cfg()
2634 brcmnand_wr_corr_thresh(host, DIV_ROUND_UP(chip->ecc.strength * 3, 4)); in brcmnand_set_cfg()
2643 "%lluMiB total, %uKiB blocks, %u%s pages, %uB OOB, %u-bit", in brcmnand_print_cfg()
2644 (unsigned long long)cfg->device_size >> 20, in brcmnand_print_cfg()
2645 cfg->block_size >> 10, in brcmnand_print_cfg()
2646 cfg->page_size >= 1024 ? cfg->page_size >> 10 : cfg->page_size, in brcmnand_print_cfg()
2647 cfg->page_size >= 1024 ? "KiB" : "B", in brcmnand_print_cfg()
2648 cfg->spare_area_size, cfg->device_width); in brcmnand_print_cfg()
2651 if (is_hamming_ecc(host->ctrl, cfg)) in brcmnand_print_cfg()
2653 else if (cfg->sector_size_1k) in brcmnand_print_cfg()
2654 sprintf(buf, ", BCH-%u (1KiB sector)", cfg->ecc_level << 1); in brcmnand_print_cfg()
2656 sprintf(buf, ", BCH-%u", cfg->ecc_level); in brcmnand_print_cfg()
2661 * roundup(log2(size / page-size) / 8)
2663 * NB: the following does not "round up" for non-power-of-2 'size'; but this is
2668 return ALIGN(ilog2(size) - ilog2(writesize), 8) >> 3; in get_blk_adr_bytes()
2673 struct mtd_info *mtd = nand_to_mtd(&host->chip); in brcmnand_setup_dev()
2674 struct nand_chip *chip = &host->chip; in brcmnand_setup_dev()
2676 nanddev_get_ecc_requirements(&chip->base); in brcmnand_setup_dev()
2678 nanddev_get_memorg(&chip->base); in brcmnand_setup_dev()
2679 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_setup_dev()
2680 struct brcmnand_cfg *cfg = &host->hwcfg; in brcmnand_setup_dev()
2688 use_strap = of_property_read_bool(np, "brcm,nand-ecc-use-strap"); in brcmnand_setup_dev()
2691 * Either nand-ecc-xxx or brcm,nand-ecc-use-strap can be set. Error out in brcmnand_setup_dev()
2694 if (chip->ecc.strength && use_strap) { in brcmnand_setup_dev()
2695 dev_err(ctrl->dev, in brcmnand_setup_dev()
2697 return -EINVAL; in brcmnand_setup_dev()
2703 ret = of_property_read_u32(np, "brcm,nand-oob-sector-size", in brcmnand_setup_dev()
2707 cfg->spare_area_size = brcmnand_get_spare_size(host); in brcmnand_setup_dev()
2710 cfg->spare_area_size = mtd->oobsize / in brcmnand_setup_dev()
2711 (mtd->writesize >> FC_SHIFT); in brcmnand_setup_dev()
2713 cfg->spare_area_size = oob_sector; in brcmnand_setup_dev()
2715 if (cfg->spare_area_size > ctrl->max_oob) in brcmnand_setup_dev()
2716 cfg->spare_area_size = ctrl->max_oob; in brcmnand_setup_dev()
2721 mtd->oobsize = cfg->spare_area_size * (mtd->writesize >> FC_SHIFT); in brcmnand_setup_dev()
2722 memorg->oobsize = mtd->oobsize; in brcmnand_setup_dev()
2724 cfg->device_size = mtd->size; in brcmnand_setup_dev()
2725 cfg->block_size = mtd->erasesize; in brcmnand_setup_dev()
2726 cfg->page_size = mtd->writesize; in brcmnand_setup_dev()
2727 cfg->device_width = (chip->options & NAND_BUSWIDTH_16) ? 16 : 8; in brcmnand_setup_dev()
2728 cfg->col_adr_bytes = 2; in brcmnand_setup_dev()
2729 cfg->blk_adr_bytes = get_blk_adr_bytes(mtd->size, mtd->writesize); in brcmnand_setup_dev()
2731 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) { in brcmnand_setup_dev()
2732 dev_err(ctrl->dev, "only HW ECC supported; selected: %d\n", in brcmnand_setup_dev()
2733 chip->ecc.engine_type); in brcmnand_setup_dev()
2734 return -EINVAL; in brcmnand_setup_dev()
2737 if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN) { in brcmnand_setup_dev()
2738 if (chip->ecc.strength == 1 && chip->ecc.size == 512) in brcmnand_setup_dev()
2739 /* Default to Hamming for 1-bit ECC, if unspecified */ in brcmnand_setup_dev()
2740 chip->ecc.algo = NAND_ECC_ALGO_HAMMING; in brcmnand_setup_dev()
2743 chip->ecc.algo = NAND_ECC_ALGO_BCH; in brcmnand_setup_dev()
2746 if (chip->ecc.algo == NAND_ECC_ALGO_HAMMING && in brcmnand_setup_dev()
2747 (chip->ecc.strength != 1 || chip->ecc.size != 512)) { in brcmnand_setup_dev()
2748 dev_err(ctrl->dev, "invalid Hamming params: %d bits per %d bytes\n", in brcmnand_setup_dev()
2749 chip->ecc.strength, chip->ecc.size); in brcmnand_setup_dev()
2750 return -EINVAL; in brcmnand_setup_dev()
2753 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_NONE && in brcmnand_setup_dev()
2754 (!chip->ecc.size || !chip->ecc.strength)) { in brcmnand_setup_dev()
2755 if (requirements->step_size && requirements->strength) { in brcmnand_setup_dev()
2757 chip->ecc.size = requirements->step_size; in brcmnand_setup_dev()
2758 chip->ecc.strength = requirements->strength; in brcmnand_setup_dev()
2759 dev_info(ctrl->dev, "Using ECC step-size %d, strength %d\n", in brcmnand_setup_dev()
2760 chip->ecc.size, chip->ecc.strength); in brcmnand_setup_dev()
2764 switch (chip->ecc.size) { in brcmnand_setup_dev()
2766 if (chip->ecc.algo == NAND_ECC_ALGO_HAMMING) in brcmnand_setup_dev()
2767 cfg->ecc_level = 15; in brcmnand_setup_dev()
2769 cfg->ecc_level = chip->ecc.strength; in brcmnand_setup_dev()
2770 cfg->sector_size_1k = 0; in brcmnand_setup_dev()
2773 if (!(ctrl->features & BRCMNAND_HAS_1K_SECTORS)) { in brcmnand_setup_dev()
2774 dev_err(ctrl->dev, "1KB sectors not supported\n"); in brcmnand_setup_dev()
2775 return -EINVAL; in brcmnand_setup_dev()
2777 if (chip->ecc.strength & 0x1) { in brcmnand_setup_dev()
2778 dev_err(ctrl->dev, in brcmnand_setup_dev()
2780 return -EINVAL; in brcmnand_setup_dev()
2783 cfg->ecc_level = chip->ecc.strength >> 1; in brcmnand_setup_dev()
2784 cfg->sector_size_1k = 1; in brcmnand_setup_dev()
2787 dev_err(ctrl->dev, "unsupported ECC size: %d\n", in brcmnand_setup_dev()
2788 chip->ecc.size); in brcmnand_setup_dev()
2789 return -EINVAL; in brcmnand_setup_dev()
2792 cfg->ful_adr_bytes = cfg->blk_adr_bytes; in brcmnand_setup_dev()
2793 if (mtd->writesize > 512) in brcmnand_setup_dev()
2794 cfg->ful_adr_bytes += cfg->col_adr_bytes; in brcmnand_setup_dev()
2796 cfg->ful_adr_bytes += 1; in brcmnand_setup_dev()
2805 dev_info(ctrl->dev, "detected %s\n", msg); in brcmnand_setup_dev()
2808 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL); in brcmnand_setup_dev()
2814 if (ctrl->nand_version >= 0x0702) in brcmnand_setup_dev()
2817 if (ctrl->features & BRCMNAND_HAS_PREFETCH) in brcmnand_setup_dev()
2831 chip->options |= NAND_NO_SUBPAGE_WRITE; in brcmnand_attach_chip()
2837 chip->options |= NAND_USES_DMA; in brcmnand_attach_chip()
2839 if (chip->bbt_options & NAND_BBT_USE_FLASH) in brcmnand_attach_chip()
2840 chip->bbt_options |= NAND_BBT_NO_OOB; in brcmnand_attach_chip()
2843 return -ENXIO; in brcmnand_attach_chip()
2845 chip->ecc.size = host->hwcfg.sector_size_1k ? 1024 : 512; in brcmnand_attach_chip()
2848 mtd->bitflip_threshold = 1; in brcmnand_attach_chip()
2853 if (is_hamming_ecc(host->ctrl, &host->hwcfg)) { in brcmnand_attach_chip()
2854 chip->ecc.write_oob = brcmnand_write_oob_raw; in brcmnand_attach_chip()
2855 chip->ecc.read_oob = brcmnand_read_oob_raw; in brcmnand_attach_chip()
2869 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_init_cs()
2870 struct device *dev = ctrl->dev; in brcmnand_init_cs()
2876 mtd = nand_to_mtd(&host->chip); in brcmnand_init_cs()
2877 chip = &host->chip; in brcmnand_init_cs()
2880 mtd->name = devm_kasprintf(dev, GFP_KERNEL, "brcmnand.%d", in brcmnand_init_cs()
2881 host->cs); in brcmnand_init_cs()
2882 if (!mtd->name) in brcmnand_init_cs()
2883 return -ENOMEM; in brcmnand_init_cs()
2885 mtd->owner = THIS_MODULE; in brcmnand_init_cs()
2886 mtd->dev.parent = dev; in brcmnand_init_cs()
2888 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; in brcmnand_init_cs()
2889 chip->ecc.read_page = brcmnand_read_page; in brcmnand_init_cs()
2890 chip->ecc.write_page = brcmnand_write_page; in brcmnand_init_cs()
2891 chip->ecc.read_page_raw = brcmnand_read_page_raw; in brcmnand_init_cs()
2892 chip->ecc.write_page_raw = brcmnand_write_page_raw; in brcmnand_init_cs()
2893 chip->ecc.write_oob_raw = brcmnand_write_oob_raw; in brcmnand_init_cs()
2894 chip->ecc.read_oob_raw = brcmnand_read_oob_raw; in brcmnand_init_cs()
2895 chip->ecc.read_oob = brcmnand_read_oob; in brcmnand_init_cs()
2896 chip->ecc.write_oob = brcmnand_write_oob; in brcmnand_init_cs()
2898 chip->controller = &ctrl->controller; in brcmnand_init_cs()
2899 ctrl->controller.controller_wp = 1; in brcmnand_init_cs()
2906 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG); in brcmnand_init_cs()
2924 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_save_restore_cs_config()
2925 u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG); in brcmnand_save_restore_cs_config()
2926 u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_save_restore_cs_config()
2928 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_save_restore_cs_config()
2930 u16 t1_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING1); in brcmnand_save_restore_cs_config()
2931 u16 t2_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING2); in brcmnand_save_restore_cs_config()
2934 nand_writereg(ctrl, cfg_offs, host->hwcfg.config); in brcmnand_save_restore_cs_config()
2937 host->hwcfg.config_ext); in brcmnand_save_restore_cs_config()
2938 nand_writereg(ctrl, acc_control_offs, host->hwcfg.acc_control); in brcmnand_save_restore_cs_config()
2939 nand_writereg(ctrl, t1_offs, host->hwcfg.timing_1); in brcmnand_save_restore_cs_config()
2940 nand_writereg(ctrl, t2_offs, host->hwcfg.timing_2); in brcmnand_save_restore_cs_config()
2942 host->hwcfg.config = nand_readreg(ctrl, cfg_offs); in brcmnand_save_restore_cs_config()
2944 host->hwcfg.config_ext = in brcmnand_save_restore_cs_config()
2946 host->hwcfg.acc_control = nand_readreg(ctrl, acc_control_offs); in brcmnand_save_restore_cs_config()
2947 host->hwcfg.timing_1 = nand_readreg(ctrl, t1_offs); in brcmnand_save_restore_cs_config()
2948 host->hwcfg.timing_2 = nand_readreg(ctrl, t2_offs); in brcmnand_save_restore_cs_config()
2957 list_for_each_entry(host, &ctrl->host_list, node) in brcmnand_suspend()
2960 ctrl->nand_cs_nand_select = brcmnand_read_reg(ctrl, BRCMNAND_CS_SELECT); in brcmnand_suspend()
2961 ctrl->nand_cs_nand_xor = brcmnand_read_reg(ctrl, BRCMNAND_CS_XOR); in brcmnand_suspend()
2962 ctrl->corr_stat_threshold = in brcmnand_suspend()
2966 ctrl->flash_dma_mode = flash_dma_readl(ctrl, FLASH_DMA_MODE); in brcmnand_suspend()
2968 ctrl->edu_config = edu_readl(ctrl, EDU_CONFIG); in brcmnand_suspend()
2979 flash_dma_writel(ctrl, FLASH_DMA_MODE, ctrl->flash_dma_mode); in brcmnand_resume()
2984 ctrl->edu_config = edu_readl(ctrl, EDU_CONFIG); in brcmnand_resume()
2985 edu_writel(ctrl, EDU_CONFIG, ctrl->edu_config); in brcmnand_resume()
2990 brcmnand_write_reg(ctrl, BRCMNAND_CS_SELECT, ctrl->nand_cs_nand_select); in brcmnand_resume()
2991 brcmnand_write_reg(ctrl, BRCMNAND_CS_XOR, ctrl->nand_cs_nand_xor); in brcmnand_resume()
2993 ctrl->corr_stat_threshold); in brcmnand_resume()
2994 if (ctrl->soc) { in brcmnand_resume()
2995 /* Clear/re-enable interrupt */ in brcmnand_resume()
2996 ctrl->soc->ctlrdy_ack(ctrl->soc); in brcmnand_resume()
2997 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true); in brcmnand_resume()
3000 list_for_each_entry(host, &ctrl->host_list, node) { in brcmnand_resume()
3001 struct nand_chip *chip = &host->chip; in brcmnand_resume()
3005 /* Reset the chip, required by some chips after power-up */ in brcmnand_resume()
3019 { .compatible = "brcm,brcmnand-v2.1" },
3020 { .compatible = "brcm,brcmnand-v2.2" },
3021 { .compatible = "brcm,brcmnand-v4.0" },
3022 { .compatible = "brcm,brcmnand-v5.0" },
3023 { .compatible = "brcm,brcmnand-v6.0" },
3024 { .compatible = "brcm,brcmnand-v6.1" },
3025 { .compatible = "brcm,brcmnand-v6.2" },
3026 { .compatible = "brcm,brcmnand-v7.0" },
3027 { .compatible = "brcm,brcmnand-v7.1" },
3028 { .compatible = "brcm,brcmnand-v7.2" },
3029 { .compatible = "brcm,brcmnand-v7.3" },
3039 struct device *dev = &pdev->dev; in brcmnand_edu_setup()
3040 struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev); in brcmnand_edu_setup()
3044 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-edu"); in brcmnand_edu_setup()
3046 ctrl->edu_base = devm_ioremap_resource(dev, res); in brcmnand_edu_setup()
3047 if (IS_ERR(ctrl->edu_base)) in brcmnand_edu_setup()
3048 return PTR_ERR(ctrl->edu_base); in brcmnand_edu_setup()
3050 ctrl->edu_offsets = edu_regs; in brcmnand_edu_setup()
3059 ctrl->edu_irq = platform_get_irq_optional(pdev, 1); in brcmnand_edu_setup()
3060 if (ctrl->edu_irq < 0) { in brcmnand_edu_setup()
3064 ret = devm_request_irq(dev, ctrl->edu_irq, in brcmnand_edu_setup()
3066 "brcmnand-edu", ctrl); in brcmnand_edu_setup()
3068 dev_err(ctrl->dev, "can't allocate IRQ %d: error %d\n", in brcmnand_edu_setup()
3069 ctrl->edu_irq, ret); in brcmnand_edu_setup()
3074 ctrl->edu_irq); in brcmnand_edu_setup()
3083 struct brcmnand_platform_data *pd = dev_get_platdata(&pdev->dev); in brcmnand_probe()
3084 struct device *dev = &pdev->dev; in brcmnand_probe()
3085 struct device_node *dn = dev->of_node, *child; in brcmnand_probe()
3092 return -ENODEV; in brcmnand_probe()
3096 return -ENOMEM; in brcmnand_probe()
3099 ctrl->dev = dev; in brcmnand_probe()
3100 ctrl->soc = soc; in brcmnand_probe()
3103 * that a non-memory mapped IO access path must be used in brcmnand_probe()
3105 if (brcmnand_soc_has_ops(ctrl->soc)) in brcmnand_probe()
3108 init_completion(&ctrl->done); in brcmnand_probe()
3109 init_completion(&ctrl->dma_done); in brcmnand_probe()
3110 init_completion(&ctrl->edu_done); in brcmnand_probe()
3111 nand_controller_init(&ctrl->controller); in brcmnand_probe()
3112 ctrl->controller.ops = &brcmnand_controller_ops; in brcmnand_probe()
3113 INIT_LIST_HEAD(&ctrl->host_list); in brcmnand_probe()
3117 ctrl->nand_base = devm_ioremap_resource(dev, res); in brcmnand_probe()
3118 if (IS_ERR(ctrl->nand_base) && !brcmnand_soc_has_ops(soc)) in brcmnand_probe()
3119 return PTR_ERR(ctrl->nand_base); in brcmnand_probe()
3122 ctrl->clk = devm_clk_get(dev, "nand"); in brcmnand_probe()
3123 if (!IS_ERR(ctrl->clk)) { in brcmnand_probe()
3124 ret = clk_prepare_enable(ctrl->clk); in brcmnand_probe()
3128 ret = PTR_ERR(ctrl->clk); in brcmnand_probe()
3129 if (ret == -EPROBE_DEFER) in brcmnand_probe()
3132 ctrl->clk = NULL; in brcmnand_probe()
3144 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand-cache"); in brcmnand_probe()
3146 ctrl->nand_fc = devm_ioremap_resource(dev, res); in brcmnand_probe()
3147 if (IS_ERR(ctrl->nand_fc)) { in brcmnand_probe()
3148 ret = PTR_ERR(ctrl->nand_fc); in brcmnand_probe()
3152 ctrl->nand_fc = ctrl->nand_base + in brcmnand_probe()
3153 ctrl->reg_offsets[BRCMNAND_FC_BASE]; in brcmnand_probe()
3157 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-dma"); in brcmnand_probe()
3159 ctrl->flash_dma_base = devm_ioremap_resource(dev, res); in brcmnand_probe()
3160 if (IS_ERR(ctrl->flash_dma_base)) { in brcmnand_probe()
3161 ret = PTR_ERR(ctrl->flash_dma_base); in brcmnand_probe()
3168 ret = -EIO; in brcmnand_probe()
3169 if (ctrl->nand_version >= 0x0700) in brcmnand_probe()
3170 ret = dma_set_mask_and_coherent(&pdev->dev, in brcmnand_probe()
3173 ret = dma_set_mask_and_coherent(&pdev->dev, in brcmnand_probe()
3178 /* linked-list and stop on error */ in brcmnand_probe()
3183 ctrl->dma_desc = dmam_alloc_coherent(dev, in brcmnand_probe()
3184 sizeof(*ctrl->dma_desc), in brcmnand_probe()
3185 &ctrl->dma_pa, GFP_KERNEL); in brcmnand_probe()
3186 if (!ctrl->dma_desc) { in brcmnand_probe()
3187 ret = -ENOMEM; in brcmnand_probe()
3191 ctrl->dma_irq = platform_get_irq(pdev, 1); in brcmnand_probe()
3192 if ((int)ctrl->dma_irq < 0) { in brcmnand_probe()
3194 ret = -ENODEV; in brcmnand_probe()
3198 ret = devm_request_irq(dev, ctrl->dma_irq, in brcmnand_probe()
3203 ctrl->dma_irq, ret); in brcmnand_probe()
3209 ctrl->dma_trans = brcmnand_dma_trans; in brcmnand_probe()
3217 ctrl->dma_trans = brcmnand_edu_trans; in brcmnand_probe()
3227 if (of_property_read_bool(dn, "brcm,wp-not-connected")) in brcmnand_probe()
3230 if (ctrl->features & BRCMNAND_HAS_WP) { in brcmnand_probe()
3239 ctrl->irq = platform_get_irq_optional(pdev, 0); in brcmnand_probe()
3240 if (ctrl->irq > 0) { in brcmnand_probe()
3246 ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0, in brcmnand_probe()
3250 ctrl->soc->ctlrdy_ack(ctrl->soc); in brcmnand_probe()
3251 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true); in brcmnand_probe()
3254 ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0, in brcmnand_probe()
3259 ctrl->irq, ret); in brcmnand_probe()
3270 ret = -ENOMEM; in brcmnand_probe()
3273 host->pdev = pdev; in brcmnand_probe()
3274 host->ctrl = ctrl; in brcmnand_probe()
3276 ret = of_property_read_u32(child, "reg", &host->cs); in brcmnand_probe()
3278 dev_err(dev, "can't get chip-select\n"); in brcmnand_probe()
3283 nand_set_flash_node(&host->chip, child); in brcmnand_probe()
3287 if (ret == -EPROBE_DEFER) { in brcmnand_probe()
3292 continue; /* Try all chip-selects */ in brcmnand_probe()
3295 list_add_tail(&host->node, &ctrl->host_list); in brcmnand_probe()
3299 if (!list_empty(&ctrl->host_list)) in brcmnand_probe()
3303 ret = -ENODEV; in brcmnand_probe()
3310 ret = -ENOMEM; in brcmnand_probe()
3313 host->pdev = pdev; in brcmnand_probe()
3314 host->ctrl = ctrl; in brcmnand_probe()
3315 host->cs = pd->chip_select; in brcmnand_probe()
3316 host->chip.ecc.size = pd->ecc_stepsize; in brcmnand_probe()
3317 host->chip.ecc.strength = pd->ecc_strength; in brcmnand_probe()
3319 ret = brcmnand_init_cs(host, pd->part_probe_types); in brcmnand_probe()
3323 list_add_tail(&host->node, &ctrl->host_list); in brcmnand_probe()
3325 /* No chip-selects could initialize properly */ in brcmnand_probe()
3326 if (list_empty(&ctrl->host_list)) { in brcmnand_probe()
3327 ret = -ENODEV; in brcmnand_probe()
3334 clk_disable_unprepare(ctrl->clk); in brcmnand_probe()
3342 struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev); in brcmnand_remove()
3347 list_for_each_entry(host, &ctrl->host_list, node) { in brcmnand_remove()
3348 chip = &host->chip; in brcmnand_remove()
3354 clk_disable_unprepare(ctrl->clk); in brcmnand_remove()
3356 dev_set_drvdata(&pdev->dev, NULL); in brcmnand_remove()