Lines Matching +full:gpio +full:- +full:op +full:- +full:cfg
1 // SPDX-License-Identifier: GPL-2.0
6 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
23 * Derived from Das U-Boot source code
24 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
38 * - atmel_nand_: all generic structures/functions
39 * - atmel_smc_nand_: all structures/functions specific to the SMC interface
41 * - atmel_hsmc_nand_: all structures/functions specific to the HSMC interface
43 * - atmel_nfc_: all structures/functions used to manipulate the NFC sub-block
45 * - <soc>_nand_: all SoC specific structures/functions
49 #include <linux/dma-mapping.h>
52 #include <linux/gpio/consumer.h>
55 #include <linux/mfd/syscon/atmel-matrix.h>
56 #include <linux/mfd/syscon/atmel-smc.h>
65 #include <soc/at91/atmel-sfr.h>
79 #define ATMEL_HSMC_NFC_CFG_PAGESIZE(x) (fls((x) / 512) - 1)
143 struct gpio_desc *gpio; member
206 const struct nand_operation *op, bool check_only);
262 struct atmel_nfc_op op; member
264 u32 cfg; member
278 static bool atmel_nfc_op_done(struct atmel_nfc_op *op, u32 status) in atmel_nfc_op_done() argument
280 op->errors |= status & ATMEL_HSMC_NFC_SR_ERRORS; in atmel_nfc_op_done()
281 op->wait ^= status & op->wait; in atmel_nfc_op_done()
283 return !op->wait || op->errors; in atmel_nfc_op_done()
292 regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &sr); in atmel_nfc_interrupt()
294 rcvd = sr & (nc->op.wait | ATMEL_HSMC_NFC_SR_ERRORS); in atmel_nfc_interrupt()
295 done = atmel_nfc_op_done(&nc->op, sr); in atmel_nfc_interrupt()
298 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, rcvd); in atmel_nfc_interrupt()
301 complete(&nc->complete); in atmel_nfc_interrupt()
317 ret = regmap_read_poll_timeout(nc->base.smc, in atmel_nfc_wait()
319 atmel_nfc_op_done(&nc->op, in atmel_nfc_wait()
323 init_completion(&nc->complete); in atmel_nfc_wait()
324 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IER, in atmel_nfc_wait()
325 nc->op.wait | ATMEL_HSMC_NFC_SR_ERRORS); in atmel_nfc_wait()
326 ret = wait_for_completion_timeout(&nc->complete, in atmel_nfc_wait()
329 ret = -ETIMEDOUT; in atmel_nfc_wait()
333 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff); in atmel_nfc_wait()
336 if (nc->op.errors & ATMEL_HSMC_NFC_SR_DTOE) { in atmel_nfc_wait()
337 dev_err(nc->base.dev, "Waiting NAND R/B Timeout\n"); in atmel_nfc_wait()
338 ret = -ETIMEDOUT; in atmel_nfc_wait()
341 if (nc->op.errors & ATMEL_HSMC_NFC_SR_UNDEF) { in atmel_nfc_wait()
342 dev_err(nc->base.dev, "Access to an undefined area\n"); in atmel_nfc_wait()
343 ret = -EIO; in atmel_nfc_wait()
346 if (nc->op.errors & ATMEL_HSMC_NFC_SR_AWB) { in atmel_nfc_wait()
347 dev_err(nc->base.dev, "Access while busy\n"); in atmel_nfc_wait()
348 ret = -EIO; in atmel_nfc_wait()
351 if (nc->op.errors & ATMEL_HSMC_NFC_SR_NFCASE) { in atmel_nfc_wait()
352 dev_err(nc->base.dev, "Wrong access size\n"); in atmel_nfc_wait()
353 ret = -EIO; in atmel_nfc_wait()
375 buf_dma = dma_map_single(nc->dev, buf, len, dir); in atmel_nand_dma_transfer()
376 if (dma_mapping_error(nc->dev, dev_dma)) { in atmel_nand_dma_transfer()
377 dev_err(nc->dev, in atmel_nand_dma_transfer()
390 tx = dmaengine_prep_dma_memcpy(nc->dmac, dst_dma, src_dma, len, in atmel_nand_dma_transfer()
393 dev_err(nc->dev, "Failed to prepare DMA memcpy\n"); in atmel_nand_dma_transfer()
397 tx->callback = atmel_nand_dma_transfer_finished; in atmel_nand_dma_transfer()
398 tx->callback_param = &finished; in atmel_nand_dma_transfer()
402 dev_err(nc->dev, "Failed to do DMA tx_submit\n"); in atmel_nand_dma_transfer()
406 dma_async_issue_pending(nc->dmac); in atmel_nand_dma_transfer()
408 dma_unmap_single(nc->dev, buf_dma, len, dir); in atmel_nand_dma_transfer()
413 dma_unmap_single(nc->dev, buf_dma, len, dir); in atmel_nand_dma_transfer()
416 dev_dbg(nc->dev, "Fall back to CPU I/O\n"); in atmel_nand_dma_transfer()
418 return -EIO; in atmel_nand_dma_transfer()
423 u8 *addrs = nc->op.addrs; in atmel_nfc_exec_op()
424 unsigned int op = 0; in atmel_nfc_exec_op() local
428 nc->op.wait = ATMEL_HSMC_NFC_SR_CMDDONE; in atmel_nfc_exec_op()
430 for (i = 0; i < nc->op.ncmds; i++) in atmel_nfc_exec_op()
431 op |= ATMEL_NFC_CMD(i, nc->op.cmds[i]); in atmel_nfc_exec_op()
433 if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES) in atmel_nfc_exec_op()
434 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_ADDR, *addrs++); in atmel_nfc_exec_op()
436 op |= ATMEL_NFC_CSID(nc->op.cs) | in atmel_nfc_exec_op()
437 ATMEL_NFC_ACYCLE(nc->op.naddrs); in atmel_nfc_exec_op()
439 if (nc->op.ncmds > 1) in atmel_nfc_exec_op()
440 op |= ATMEL_NFC_VCMD2; in atmel_nfc_exec_op()
445 if (nc->op.data != ATMEL_NFC_NO_DATA) { in atmel_nfc_exec_op()
446 op |= ATMEL_NFC_DATAEN; in atmel_nfc_exec_op()
447 nc->op.wait |= ATMEL_HSMC_NFC_SR_XFRDONE; in atmel_nfc_exec_op()
449 if (nc->op.data == ATMEL_NFC_WRITE_DATA) in atmel_nfc_exec_op()
450 op |= ATMEL_NFC_NFCWR; in atmel_nfc_exec_op()
454 regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &val); in atmel_nfc_exec_op()
457 regmap_write(nc->io, op, addr); in atmel_nfc_exec_op()
461 dev_err(nc->base.dev, in atmel_nfc_exec_op()
465 /* Reset the op state. */ in atmel_nfc_exec_op()
466 memset(&nc->op, 0, sizeof(nc->op)); in atmel_nfc_exec_op()
476 nc = to_nand_controller(nand->base.controller); in atmel_nand_data_in()
479 * If the controller supports DMA, the buffer address is DMA-able and in atmel_nand_data_in()
483 if (nc->dmac && virt_addr_valid(buf) && in atmel_nand_data_in()
485 !atmel_nand_dma_transfer(nc, buf, nand->activecs->io.dma, len, in atmel_nand_data_in()
489 if ((nand->base.options & NAND_BUSWIDTH_16) && !force_8bit) in atmel_nand_data_in()
490 ioread16_rep(nand->activecs->io.virt, buf, len / 2); in atmel_nand_data_in()
492 ioread8_rep(nand->activecs->io.virt, buf, len); in atmel_nand_data_in()
500 nc = to_nand_controller(nand->base.controller); in atmel_nand_data_out()
503 * If the controller supports DMA, the buffer address is DMA-able and in atmel_nand_data_out()
507 if (nc->dmac && virt_addr_valid(buf) && in atmel_nand_data_out()
509 !atmel_nand_dma_transfer(nc, (void *)buf, nand->activecs->io.dma, in atmel_nand_data_out()
513 if ((nand->base.options & NAND_BUSWIDTH_16) && !force_8bit) in atmel_nand_data_out()
514 iowrite16_rep(nand->activecs->io.virt, buf, len / 2); in atmel_nand_data_out()
516 iowrite8_rep(nand->activecs->io.virt, buf, len); in atmel_nand_data_out()
521 if (nand->activecs->rb.type == ATMEL_NAND_NO_RB) in atmel_nand_waitrdy()
522 return nand_soft_waitrdy(&nand->base, timeout_ms); in atmel_nand_waitrdy()
524 return nand_gpio_waitrdy(&nand->base, nand->activecs->rb.gpio, in atmel_nand_waitrdy()
534 if (nand->activecs->rb.type != ATMEL_NAND_NATIVE_RB) in atmel_hsmc_nand_waitrdy()
537 nc = to_hsmc_nand_controller(nand->base.controller); in atmel_hsmc_nand_waitrdy()
538 mask = ATMEL_HSMC_NFC_SR_RBEDGE(nand->activecs->rb.id); in atmel_hsmc_nand_waitrdy()
539 return regmap_read_poll_timeout_atomic(nc->base.smc, ATMEL_HSMC_NFC_SR, in atmel_hsmc_nand_waitrdy()
547 nand->activecs = &nand->cs[cs]; in atmel_nand_select_target()
553 struct mtd_info *mtd = nand_to_mtd(&nand->base); in atmel_hsmc_nand_select_target()
555 u32 cfg = ATMEL_HSMC_NFC_CFG_PAGESIZE(mtd->writesize) | in atmel_hsmc_nand_select_target() local
556 ATMEL_HSMC_NFC_CFG_SPARESIZE(mtd->oobsize) | in atmel_hsmc_nand_select_target()
559 nand->activecs = &nand->cs[cs]; in atmel_hsmc_nand_select_target()
560 nc = to_hsmc_nand_controller(nand->base.controller); in atmel_hsmc_nand_select_target()
561 if (nc->cfg == cfg) in atmel_hsmc_nand_select_target()
564 regmap_update_bits(nc->base.smc, ATMEL_HSMC_NFC_CFG, in atmel_hsmc_nand_select_target()
569 cfg); in atmel_hsmc_nand_select_target()
570 nc->cfg = cfg; in atmel_hsmc_nand_select_target()
579 nc = to_nand_controller(nand->base.controller); in atmel_smc_nand_exec_instr()
580 switch (instr->type) { in atmel_smc_nand_exec_instr()
582 writeb(instr->ctx.cmd.opcode, in atmel_smc_nand_exec_instr()
583 nand->activecs->io.virt + nc->caps->cle_offs); in atmel_smc_nand_exec_instr()
586 for (i = 0; i < instr->ctx.addr.naddrs; i++) in atmel_smc_nand_exec_instr()
587 writeb(instr->ctx.addr.addrs[i], in atmel_smc_nand_exec_instr()
588 nand->activecs->io.virt + nc->caps->ale_offs); in atmel_smc_nand_exec_instr()
591 atmel_nand_data_in(nand, instr->ctx.data.buf.in, in atmel_smc_nand_exec_instr()
592 instr->ctx.data.len, in atmel_smc_nand_exec_instr()
593 instr->ctx.data.force_8bit); in atmel_smc_nand_exec_instr()
596 atmel_nand_data_out(nand, instr->ctx.data.buf.out, in atmel_smc_nand_exec_instr()
597 instr->ctx.data.len, in atmel_smc_nand_exec_instr()
598 instr->ctx.data.force_8bit); in atmel_smc_nand_exec_instr()
602 instr->ctx.waitrdy.timeout_ms); in atmel_smc_nand_exec_instr()
607 return -EINVAL; in atmel_smc_nand_exec_instr()
611 const struct nand_operation *op, in atmel_smc_nand_exec_op() argument
620 atmel_nand_select_target(nand, op->cs); in atmel_smc_nand_exec_op()
621 gpiod_set_value(nand->activecs->csgpio, 0); in atmel_smc_nand_exec_op()
622 for (i = 0; i < op->ninstrs; i++) { in atmel_smc_nand_exec_op()
623 ret = atmel_smc_nand_exec_instr(nand, &op->instrs[i]); in atmel_smc_nand_exec_op()
627 gpiod_set_value(nand->activecs->csgpio, 1); in atmel_smc_nand_exec_op()
639 nc = to_hsmc_nand_controller(chip->controller); in atmel_hsmc_exec_cmd_addr()
641 nc->op.cs = nand->activecs->id; in atmel_hsmc_exec_cmd_addr()
642 for (i = 0; i < subop->ninstrs; i++) { in atmel_hsmc_exec_cmd_addr()
643 const struct nand_op_instr *instr = &subop->instrs[i]; in atmel_hsmc_exec_cmd_addr()
645 if (instr->type == NAND_OP_CMD_INSTR) { in atmel_hsmc_exec_cmd_addr()
646 nc->op.cmds[nc->op.ncmds++] = instr->ctx.cmd.opcode; in atmel_hsmc_exec_cmd_addr()
652 nc->op.addrs[nc->op.naddrs] = instr->ctx.addr.addrs[j]; in atmel_hsmc_exec_cmd_addr()
653 nc->op.naddrs++; in atmel_hsmc_exec_cmd_addr()
663 const struct nand_op_instr *instr = subop->instrs; in atmel_hsmc_exec_rw()
666 if (instr->type == NAND_OP_DATA_IN_INSTR) in atmel_hsmc_exec_rw()
667 atmel_nand_data_in(nand, instr->ctx.data.buf.in, in atmel_hsmc_exec_rw()
668 instr->ctx.data.len, in atmel_hsmc_exec_rw()
669 instr->ctx.data.force_8bit); in atmel_hsmc_exec_rw()
671 atmel_nand_data_out(nand, instr->ctx.data.buf.out, in atmel_hsmc_exec_rw()
672 instr->ctx.data.len, in atmel_hsmc_exec_rw()
673 instr->ctx.data.force_8bit); in atmel_hsmc_exec_rw()
681 const struct nand_op_instr *instr = subop->instrs; in atmel_hsmc_exec_waitrdy()
684 return atmel_hsmc_nand_waitrdy(nand, instr->ctx.waitrdy.timeout_ms); in atmel_hsmc_exec_waitrdy()
701 const struct nand_operation *op, in atmel_hsmc_nand_exec_op() argument
707 return nand_op_parser_exec_op(&nand->base, in atmel_hsmc_nand_exec_op()
708 &atmel_hsmc_op_parser, op, true); in atmel_hsmc_nand_exec_op()
710 atmel_hsmc_nand_select_target(nand, op->cs); in atmel_hsmc_nand_exec_op()
711 ret = nand_op_parser_exec_op(&nand->base, &atmel_hsmc_op_parser, op, in atmel_hsmc_nand_exec_op()
722 int ret = -EIO; in atmel_nfc_copy_to_sram()
724 nc = to_hsmc_nand_controller(chip->controller); in atmel_nfc_copy_to_sram()
726 if (nc->base.dmac) in atmel_nfc_copy_to_sram()
727 ret = atmel_nand_dma_transfer(&nc->base, (void *)buf, in atmel_nfc_copy_to_sram()
728 nc->sram.dma, mtd->writesize, in atmel_nfc_copy_to_sram()
733 memcpy_toio(nc->sram.virt, buf, mtd->writesize); in atmel_nfc_copy_to_sram()
736 memcpy_toio(nc->sram.virt + mtd->writesize, chip->oob_poi, in atmel_nfc_copy_to_sram()
737 mtd->oobsize); in atmel_nfc_copy_to_sram()
745 int ret = -EIO; in atmel_nfc_copy_from_sram()
747 nc = to_hsmc_nand_controller(chip->controller); in atmel_nfc_copy_from_sram()
749 if (nc->base.dmac) in atmel_nfc_copy_from_sram()
750 ret = atmel_nand_dma_transfer(&nc->base, buf, nc->sram.dma, in atmel_nfc_copy_from_sram()
751 mtd->writesize, DMA_FROM_DEVICE); in atmel_nfc_copy_from_sram()
755 memcpy_fromio(buf, nc->sram.virt, mtd->writesize); in atmel_nfc_copy_from_sram()
758 memcpy_fromio(chip->oob_poi, nc->sram.virt + mtd->writesize, in atmel_nfc_copy_from_sram()
759 mtd->oobsize); in atmel_nfc_copy_from_sram()
767 nc = to_hsmc_nand_controller(chip->controller); in atmel_nfc_set_op_addr()
770 nc->op.addrs[nc->op.naddrs++] = column; in atmel_nfc_set_op_addr()
775 if (mtd->writesize > 512) in atmel_nfc_set_op_addr()
776 nc->op.addrs[nc->op.naddrs++] = column >> 8; in atmel_nfc_set_op_addr()
780 nc->op.addrs[nc->op.naddrs++] = page; in atmel_nfc_set_op_addr()
781 nc->op.addrs[nc->op.naddrs++] = page >> 8; in atmel_nfc_set_op_addr()
783 if (chip->options & NAND_ROW_ADDR_3) in atmel_nfc_set_op_addr()
784 nc->op.addrs[nc->op.naddrs++] = page >> 16; in atmel_nfc_set_op_addr()
788 static int atmel_nand_pmecc_enable(struct nand_chip *chip, int op, bool raw) in atmel_nand_pmecc_enable() argument
794 nc = to_nand_controller(chip->controller); in atmel_nand_pmecc_enable()
799 ret = atmel_pmecc_enable(nand->pmecc, op); in atmel_nand_pmecc_enable()
801 dev_err(nc->dev, in atmel_nand_pmecc_enable()
812 atmel_pmecc_disable(nand->pmecc); in atmel_nand_pmecc_disable()
824 nc = to_nand_controller(chip->controller); in atmel_nand_pmecc_generate_eccbytes()
829 ret = atmel_pmecc_wait_rdy(nand->pmecc); in atmel_nand_pmecc_generate_eccbytes()
831 dev_err(nc->dev, in atmel_nand_pmecc_generate_eccbytes()
838 eccbuf = chip->oob_poi + oobregion.offset; in atmel_nand_pmecc_generate_eccbytes()
840 for (i = 0; i < chip->ecc.steps; i++) { in atmel_nand_pmecc_generate_eccbytes()
841 atmel_pmecc_get_generated_eccbytes(nand->pmecc, i, in atmel_nand_pmecc_generate_eccbytes()
843 eccbuf += chip->ecc.bytes; in atmel_nand_pmecc_generate_eccbytes()
859 nc = to_nand_controller(chip->controller); in atmel_nand_pmecc_correct_data()
864 ret = atmel_pmecc_wait_rdy(nand->pmecc); in atmel_nand_pmecc_correct_data()
866 dev_err(nc->dev, in atmel_nand_pmecc_correct_data()
873 eccbuf = chip->oob_poi + oobregion.offset; in atmel_nand_pmecc_correct_data()
876 for (i = 0; i < chip->ecc.steps; i++) { in atmel_nand_pmecc_correct_data()
877 ret = atmel_pmecc_correct_sector(nand->pmecc, i, databuf, in atmel_nand_pmecc_correct_data()
879 if (ret < 0 && !atmel_pmecc_correct_erased_chunks(nand->pmecc)) in atmel_nand_pmecc_correct_data()
881 chip->ecc.size, in atmel_nand_pmecc_correct_data()
883 chip->ecc.bytes, in atmel_nand_pmecc_correct_data()
885 chip->ecc.strength); in atmel_nand_pmecc_correct_data()
888 mtd->ecc_stats.corrected += ret; in atmel_nand_pmecc_correct_data()
891 mtd->ecc_stats.failed++; in atmel_nand_pmecc_correct_data()
894 databuf += chip->ecc.size; in atmel_nand_pmecc_correct_data()
895 eccbuf += chip->ecc.bytes; in atmel_nand_pmecc_correct_data()
914 nand_write_data_op(chip, buf, mtd->writesize, false); in atmel_nand_pmecc_write_pg()
918 atmel_pmecc_disable(nand->pmecc); in atmel_nand_pmecc_write_pg()
924 nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false); in atmel_nand_pmecc_write_pg()
954 ret = nand_read_data_op(chip, buf, mtd->writesize, false, false); in atmel_nand_pmecc_read_pg()
958 ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize, false, false); in atmel_nand_pmecc_read_pg()
991 atmel_hsmc_nand_select_target(nand, chip->cur_cs); in atmel_hsmc_nand_pmecc_write_pg()
992 nc = to_hsmc_nand_controller(chip->controller); in atmel_hsmc_nand_pmecc_write_pg()
996 nc->op.cmds[0] = NAND_CMD_SEQIN; in atmel_hsmc_nand_pmecc_write_pg()
997 nc->op.ncmds = 1; in atmel_hsmc_nand_pmecc_write_pg()
999 nc->op.cs = nand->activecs->id; in atmel_hsmc_nand_pmecc_write_pg()
1000 nc->op.data = ATMEL_NFC_WRITE_DATA; in atmel_hsmc_nand_pmecc_write_pg()
1009 dev_err(nc->base.dev, in atmel_hsmc_nand_pmecc_write_pg()
1022 nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false); in atmel_hsmc_nand_pmecc_write_pg()
1052 atmel_hsmc_nand_select_target(nand, chip->cur_cs); in atmel_hsmc_nand_pmecc_read_pg()
1053 nc = to_hsmc_nand_controller(chip->controller); in atmel_hsmc_nand_pmecc_read_pg()
1058 * to the non-optimized one. in atmel_hsmc_nand_pmecc_read_pg()
1060 if (nand->activecs->rb.type != ATMEL_NAND_NATIVE_RB) in atmel_hsmc_nand_pmecc_read_pg()
1064 nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READ0; in atmel_hsmc_nand_pmecc_read_pg()
1066 if (mtd->writesize > 512) in atmel_hsmc_nand_pmecc_read_pg()
1067 nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READSTART; in atmel_hsmc_nand_pmecc_read_pg()
1070 nc->op.cs = nand->activecs->id; in atmel_hsmc_nand_pmecc_read_pg()
1071 nc->op.data = ATMEL_NFC_READ_DATA; in atmel_hsmc_nand_pmecc_read_pg()
1080 dev_err(nc->base.dev, in atmel_hsmc_nand_pmecc_read_pg()
1113 nanddev_get_ecc_requirements(&chip->base); in atmel_nand_pmecc_init()
1120 nc = to_nand_controller(chip->controller); in atmel_nand_pmecc_init()
1122 if (!nc->pmecc) { in atmel_nand_pmecc_init()
1123 dev_err(nc->dev, "HW ECC not supported\n"); in atmel_nand_pmecc_init()
1124 return -ENOTSUPP; in atmel_nand_pmecc_init()
1127 if (nc->caps->legacy_of_bindings) { in atmel_nand_pmecc_init()
1130 if (!of_property_read_u32(nc->dev->of_node, "atmel,pmecc-cap", in atmel_nand_pmecc_init()
1132 chip->ecc.strength = val; in atmel_nand_pmecc_init()
1134 if (!of_property_read_u32(nc->dev->of_node, in atmel_nand_pmecc_init()
1135 "atmel,pmecc-sector-size", in atmel_nand_pmecc_init()
1137 chip->ecc.size = val; in atmel_nand_pmecc_init()
1140 if (nanddev->ecc.user_conf.flags & NAND_ECC_MAXIMIZE_STRENGTH) in atmel_nand_pmecc_init()
1142 else if (chip->ecc.strength) in atmel_nand_pmecc_init()
1143 req.ecc.strength = chip->ecc.strength; in atmel_nand_pmecc_init()
1144 else if (requirements->strength) in atmel_nand_pmecc_init()
1145 req.ecc.strength = requirements->strength; in atmel_nand_pmecc_init()
1149 if (chip->ecc.size) in atmel_nand_pmecc_init()
1150 req.ecc.sectorsize = chip->ecc.size; in atmel_nand_pmecc_init()
1151 else if (requirements->step_size) in atmel_nand_pmecc_init()
1152 req.ecc.sectorsize = requirements->step_size; in atmel_nand_pmecc_init()
1156 req.pagesize = mtd->writesize; in atmel_nand_pmecc_init()
1157 req.oobsize = mtd->oobsize; in atmel_nand_pmecc_init()
1159 if (mtd->writesize <= 512) { in atmel_nand_pmecc_init()
1163 req.ecc.bytes = mtd->oobsize - 2; in atmel_nand_pmecc_init()
1167 nand->pmecc = atmel_pmecc_create_user(nc->pmecc, &req); in atmel_nand_pmecc_init()
1168 if (IS_ERR(nand->pmecc)) in atmel_nand_pmecc_init()
1169 return PTR_ERR(nand->pmecc); in atmel_nand_pmecc_init()
1171 chip->ecc.algo = NAND_ECC_ALGO_BCH; in atmel_nand_pmecc_init()
1172 chip->ecc.size = req.ecc.sectorsize; in atmel_nand_pmecc_init()
1173 chip->ecc.bytes = req.ecc.bytes / req.ecc.nsectors; in atmel_nand_pmecc_init()
1174 chip->ecc.strength = req.ecc.strength; in atmel_nand_pmecc_init()
1176 chip->options |= NAND_NO_SUBPAGE_WRITE; in atmel_nand_pmecc_init()
1188 nc = to_nand_controller(chip->controller); in atmel_nand_ecc_init()
1190 switch (chip->ecc.engine_type) { in atmel_nand_ecc_init()
1203 chip->ecc.read_page = atmel_nand_pmecc_read_page; in atmel_nand_ecc_init()
1204 chip->ecc.write_page = atmel_nand_pmecc_write_page; in atmel_nand_ecc_init()
1205 chip->ecc.read_page_raw = atmel_nand_pmecc_read_page_raw; in atmel_nand_ecc_init()
1206 chip->ecc.write_page_raw = atmel_nand_pmecc_write_page_raw; in atmel_nand_ecc_init()
1211 dev_err(nc->dev, "Unsupported ECC mode: %d\n", in atmel_nand_ecc_init()
1212 chip->ecc.engine_type); in atmel_nand_ecc_init()
1213 return -ENOTSUPP; in atmel_nand_ecc_init()
1227 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) in atmel_hsmc_nand_ecc_init()
1231 chip->ecc.read_page = atmel_hsmc_nand_pmecc_read_page; in atmel_hsmc_nand_ecc_init()
1232 chip->ecc.write_page = atmel_hsmc_nand_pmecc_write_page; in atmel_hsmc_nand_ecc_init()
1233 chip->ecc.read_page_raw = atmel_hsmc_nand_pmecc_read_page_raw; in atmel_hsmc_nand_ecc_init()
1234 chip->ecc.write_page_raw = atmel_hsmc_nand_pmecc_write_page_raw; in atmel_hsmc_nand_ecc_init()
1247 nc = to_nand_controller(nand->base.controller); in atmel_smc_nand_prepare_smcconf()
1251 return -ENOTSUPP; in atmel_smc_nand_prepare_smcconf()
1257 if (conf->timings.sdr.tRC_min < 30000) in atmel_smc_nand_prepare_smcconf()
1258 return -ENOTSUPP; in atmel_smc_nand_prepare_smcconf()
1262 mckperiodps = NSEC_PER_SEC / clk_get_rate(nc->mck); in atmel_smc_nand_prepare_smcconf()
1270 ncycles = DIV_ROUND_UP(conf->timings.sdr.tWP_min, mckperiodps); in atmel_smc_nand_prepare_smcconf()
1286 * NWE_SETUP = max(tCLS, tCS, tALS, tDS) - NWE_PULSE in atmel_smc_nand_prepare_smcconf()
1288 timeps = max3(conf->timings.sdr.tCLS_min, conf->timings.sdr.tCS_min, in atmel_smc_nand_prepare_smcconf()
1289 conf->timings.sdr.tALS_min); in atmel_smc_nand_prepare_smcconf()
1290 timeps = max(timeps, conf->timings.sdr.tDS_min); in atmel_smc_nand_prepare_smcconf()
1292 ncycles = ncycles > totalcycles ? ncycles - totalcycles : 0; in atmel_smc_nand_prepare_smcconf()
1305 timeps = max3(conf->timings.sdr.tCLH_min, conf->timings.sdr.tCH_min, in atmel_smc_nand_prepare_smcconf()
1306 conf->timings.sdr.tALH_min); in atmel_smc_nand_prepare_smcconf()
1307 timeps = max3(timeps, conf->timings.sdr.tDH_min, in atmel_smc_nand_prepare_smcconf()
1308 conf->timings.sdr.tWH_min); in atmel_smc_nand_prepare_smcconf()
1319 ncycles = DIV_ROUND_UP(conf->timings.sdr.tWC_min, mckperiodps); in atmel_smc_nand_prepare_smcconf()
1344 timeps = max(conf->timings.sdr.tREH_min, conf->timings.sdr.tRHOH_min); in atmel_smc_nand_prepare_smcconf()
1349 * TDF = tRHZ - NRD_HOLD in atmel_smc_nand_prepare_smcconf()
1351 ncycles = DIV_ROUND_UP(conf->timings.sdr.tRHZ_max, mckperiodps); in atmel_smc_nand_prepare_smcconf()
1352 ncycles -= totalcycles; in atmel_smc_nand_prepare_smcconf()
1365 smcconf->mode |= ATMEL_SMC_MODE_TDF(ncycles) | in atmel_smc_nand_prepare_smcconf()
1373 ncycles = DIV_ROUND_UP(conf->timings.sdr.tRP_min, mckperiodps); in atmel_smc_nand_prepare_smcconf()
1389 ncycles = DIV_ROUND_UP(conf->timings.sdr.tRC_min, mckperiodps); in atmel_smc_nand_prepare_smcconf()
1409 ncycles = DIV_ROUND_UP(conf->timings.sdr.tCLR_min, mckperiodps); in atmel_smc_nand_prepare_smcconf()
1416 ncycles = DIV_ROUND_UP(conf->timings.sdr.tADL_min, mckperiodps); in atmel_smc_nand_prepare_smcconf()
1424 * accept the -ERANGE return code. in atmel_smc_nand_prepare_smcconf()
1431 if (ret && ret != -ERANGE) in atmel_smc_nand_prepare_smcconf()
1434 ncycles = DIV_ROUND_UP(conf->timings.sdr.tAR_min, mckperiodps); in atmel_smc_nand_prepare_smcconf()
1441 ncycles = DIV_ROUND_UP(conf->timings.sdr.tRR_min, mckperiodps); in atmel_smc_nand_prepare_smcconf()
1448 ncycles = DIV_ROUND_UP(conf->timings.sdr.tWB_max, mckperiodps); in atmel_smc_nand_prepare_smcconf()
1456 smcconf->timings |= ATMEL_HSMC_TIMINGS_NFSEL; in atmel_smc_nand_prepare_smcconf()
1459 if (nand->base.options & NAND_BUSWIDTH_16) in atmel_smc_nand_prepare_smcconf()
1460 smcconf->mode |= ATMEL_SMC_MODE_DBW_16; in atmel_smc_nand_prepare_smcconf()
1463 smcconf->mode |= ATMEL_SMC_MODE_READMODE_NRD | in atmel_smc_nand_prepare_smcconf()
1478 nc = to_nand_controller(nand->base.controller); in atmel_smc_nand_setup_interface()
1487 cs = &nand->cs[csline]; in atmel_smc_nand_setup_interface()
1488 cs->smcconf = smcconf; in atmel_smc_nand_setup_interface()
1489 atmel_smc_cs_conf_apply(nc->smc, cs->id, &cs->smcconf); in atmel_smc_nand_setup_interface()
1503 nc = to_hsmc_nand_controller(nand->base.controller); in atmel_hsmc_nand_setup_interface()
1512 cs = &nand->cs[csline]; in atmel_hsmc_nand_setup_interface()
1513 cs->smcconf = smcconf; in atmel_hsmc_nand_setup_interface()
1515 if (cs->rb.type == ATMEL_NAND_NATIVE_RB) in atmel_hsmc_nand_setup_interface()
1516 cs->smcconf.timings |= ATMEL_HSMC_TIMINGS_RBNSEL(cs->rb.id); in atmel_hsmc_nand_setup_interface()
1518 atmel_hsmc_cs_conf_apply(nc->base.smc, nc->hsmc_layout, cs->id, in atmel_hsmc_nand_setup_interface()
1519 &cs->smcconf); in atmel_hsmc_nand_setup_interface()
1535 nc = to_nand_controller(nand->base.controller); in atmel_nand_setup_interface()
1537 if (csline >= nand->numcs || in atmel_nand_setup_interface()
1539 return -EINVAL; in atmel_nand_setup_interface()
1541 return nc->caps->ops->setup_interface(nand, csline, conf); in atmel_nand_setup_interface()
1545 const struct nand_operation *op, in atmel_nand_exec_op() argument
1551 nc = to_nand_controller(nand->base.controller); in atmel_nand_exec_op()
1553 return nc->caps->ops->exec_op(nand, op, check_only); in atmel_nand_exec_op()
1559 struct nand_chip *chip = &nand->base; in atmel_nand_init()
1562 mtd->dev.parent = nc->dev; in atmel_nand_init()
1563 nand->base.controller = &nc->base; in atmel_nand_init()
1565 if (!nc->mck || !nc->caps->ops->setup_interface) in atmel_nand_init()
1566 chip->options |= NAND_KEEP_TIMINGS; in atmel_nand_init()
1572 if (nc->dmac) in atmel_nand_init()
1573 chip->options |= NAND_USES_DMA; in atmel_nand_init()
1576 if (nc->pmecc) in atmel_nand_init()
1577 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; in atmel_nand_init()
1583 struct nand_chip *chip = &nand->base; in atmel_smc_nand_init()
1589 smc_nc = to_smc_nand_controller(chip->controller); in atmel_smc_nand_init()
1590 if (!smc_nc->ebi_csa_regmap) in atmel_smc_nand_init()
1594 for (i = 0; i < nand->numcs; i++) in atmel_smc_nand_init()
1595 regmap_update_bits(smc_nc->ebi_csa_regmap, in atmel_smc_nand_init()
1596 smc_nc->ebi_csa->offs, in atmel_smc_nand_init()
1597 BIT(nand->cs[i].id), BIT(nand->cs[i].id)); in atmel_smc_nand_init()
1599 if (smc_nc->ebi_csa->nfd0_on_d16) in atmel_smc_nand_init()
1600 regmap_update_bits(smc_nc->ebi_csa_regmap, in atmel_smc_nand_init()
1601 smc_nc->ebi_csa->offs, in atmel_smc_nand_init()
1602 smc_nc->ebi_csa->nfd0_on_d16, in atmel_smc_nand_init()
1603 smc_nc->ebi_csa->nfd0_on_d16); in atmel_smc_nand_init()
1608 struct nand_chip *chip = &nand->base; in atmel_nand_controller_remove_nand()
1617 list_del(&nand->node); in atmel_nand_controller_remove_nand()
1627 struct gpio_desc *gpio; in atmel_nand_create() local
1633 dev_err(nc->dev, "Missing or invalid reg property\n"); in atmel_nand_create()
1634 return ERR_PTR(-EINVAL); in atmel_nand_create()
1637 nand = devm_kzalloc(nc->dev, struct_size(nand, cs, numcs), GFP_KERNEL); in atmel_nand_create()
1639 return ERR_PTR(-ENOMEM); in atmel_nand_create()
1641 nand->numcs = numcs; in atmel_nand_create()
1643 gpio = devm_fwnode_gpiod_get(nc->dev, of_fwnode_handle(np), in atmel_nand_create()
1644 "det", GPIOD_IN, "nand-det"); in atmel_nand_create()
1645 if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) { in atmel_nand_create()
1646 dev_err(nc->dev, in atmel_nand_create()
1647 "Failed to get detect gpio (err = %ld)\n", in atmel_nand_create()
1648 PTR_ERR(gpio)); in atmel_nand_create()
1649 return ERR_CAST(gpio); in atmel_nand_create()
1652 if (!IS_ERR(gpio)) in atmel_nand_create()
1653 nand->cdgpio = gpio; in atmel_nand_create()
1661 dev_err(nc->dev, "Invalid reg property (err = %d)\n", in atmel_nand_create()
1669 dev_err(nc->dev, "Invalid reg property (err = %d)\n", in atmel_nand_create()
1674 nand->cs[i].id = val; in atmel_nand_create()
1676 nand->cs[i].io.dma = res.start; in atmel_nand_create()
1677 nand->cs[i].io.virt = devm_ioremap_resource(nc->dev, &res); in atmel_nand_create()
1678 if (IS_ERR(nand->cs[i].io.virt)) in atmel_nand_create()
1679 return ERR_CAST(nand->cs[i].io.virt); in atmel_nand_create()
1683 return ERR_PTR(-EINVAL); in atmel_nand_create()
1685 nand->cs[i].rb.type = ATMEL_NAND_NATIVE_RB; in atmel_nand_create()
1686 nand->cs[i].rb.id = val; in atmel_nand_create()
1688 gpio = devm_fwnode_gpiod_get_index(nc->dev, in atmel_nand_create()
1691 "nand-rb"); in atmel_nand_create()
1692 if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) { in atmel_nand_create()
1693 dev_err(nc->dev, in atmel_nand_create()
1694 "Failed to get R/B gpio (err = %ld)\n", in atmel_nand_create()
1695 PTR_ERR(gpio)); in atmel_nand_create()
1696 return ERR_CAST(gpio); in atmel_nand_create()
1699 if (!IS_ERR(gpio)) { in atmel_nand_create()
1700 nand->cs[i].rb.type = ATMEL_NAND_GPIO_RB; in atmel_nand_create()
1701 nand->cs[i].rb.gpio = gpio; in atmel_nand_create()
1705 gpio = devm_fwnode_gpiod_get_index(nc->dev, in atmel_nand_create()
1708 "nand-cs"); in atmel_nand_create()
1709 if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) { in atmel_nand_create()
1710 dev_err(nc->dev, in atmel_nand_create()
1711 "Failed to get CS gpio (err = %ld)\n", in atmel_nand_create()
1712 PTR_ERR(gpio)); in atmel_nand_create()
1713 return ERR_CAST(gpio); in atmel_nand_create()
1716 if (!IS_ERR(gpio)) in atmel_nand_create()
1717 nand->cs[i].csgpio = gpio; in atmel_nand_create()
1720 nand_set_flash_node(&nand->base, np); in atmel_nand_create()
1729 struct nand_chip *chip = &nand->base; in atmel_nand_controller_add_nand()
1734 if (nand->cdgpio && gpiod_get_value(nand->cdgpio)) { in atmel_nand_controller_add_nand()
1735 dev_info(nc->dev, "No SmartMedia card inserted.\n"); in atmel_nand_controller_add_nand()
1739 nc->caps->ops->nand_init(nc, nand); in atmel_nand_controller_add_nand()
1741 ret = nand_scan(chip, nand->numcs); in atmel_nand_controller_add_nand()
1743 dev_err(nc->dev, "NAND scan failed: %d\n", ret); in atmel_nand_controller_add_nand()
1749 dev_err(nc->dev, "Failed to register mtd device: %d\n", ret); in atmel_nand_controller_add_nand()
1754 list_add_tail(&nand->node, &nc->chips); in atmel_nand_controller_add_nand()
1765 list_for_each_entry_safe(nand, tmp, &nc->chips, node) { in atmel_nand_controller_remove_nands()
1777 struct device *dev = nc->dev; in atmel_nand_controller_legacy_add_nands()
1780 struct gpio_desc *gpio; in atmel_nand_controller_legacy_add_nands() local
1787 nand = devm_kzalloc(nc->dev, sizeof(*nand) + sizeof(*nand->cs), in atmel_nand_controller_legacy_add_nands()
1790 return -ENOMEM; in atmel_nand_controller_legacy_add_nands()
1792 nand->numcs = 1; in atmel_nand_controller_legacy_add_nands()
1794 nand->cs[0].io.virt = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in atmel_nand_controller_legacy_add_nands()
1795 if (IS_ERR(nand->cs[0].io.virt)) in atmel_nand_controller_legacy_add_nands()
1796 return PTR_ERR(nand->cs[0].io.virt); in atmel_nand_controller_legacy_add_nands()
1798 nand->cs[0].io.dma = res->start; in atmel_nand_controller_legacy_add_nands()
1808 nand->cs[0].id = 3; in atmel_nand_controller_legacy_add_nands()
1810 /* R/B GPIO. */ in atmel_nand_controller_legacy_add_nands()
1811 gpio = devm_gpiod_get_index_optional(dev, NULL, 0, GPIOD_IN); in atmel_nand_controller_legacy_add_nands()
1812 if (IS_ERR(gpio)) { in atmel_nand_controller_legacy_add_nands()
1813 dev_err(dev, "Failed to get R/B gpio (err = %ld)\n", in atmel_nand_controller_legacy_add_nands()
1814 PTR_ERR(gpio)); in atmel_nand_controller_legacy_add_nands()
1815 return PTR_ERR(gpio); in atmel_nand_controller_legacy_add_nands()
1818 if (gpio) { in atmel_nand_controller_legacy_add_nands()
1819 nand->cs[0].rb.type = ATMEL_NAND_GPIO_RB; in atmel_nand_controller_legacy_add_nands()
1820 nand->cs[0].rb.gpio = gpio; in atmel_nand_controller_legacy_add_nands()
1823 /* CS GPIO. */ in atmel_nand_controller_legacy_add_nands()
1824 gpio = devm_gpiod_get_index_optional(dev, NULL, 1, GPIOD_OUT_HIGH); in atmel_nand_controller_legacy_add_nands()
1825 if (IS_ERR(gpio)) { in atmel_nand_controller_legacy_add_nands()
1826 dev_err(dev, "Failed to get CS gpio (err = %ld)\n", in atmel_nand_controller_legacy_add_nands()
1827 PTR_ERR(gpio)); in atmel_nand_controller_legacy_add_nands()
1828 return PTR_ERR(gpio); in atmel_nand_controller_legacy_add_nands()
1831 nand->cs[0].csgpio = gpio; in atmel_nand_controller_legacy_add_nands()
1833 /* Card detect GPIO. */ in atmel_nand_controller_legacy_add_nands()
1834 gpio = devm_gpiod_get_index_optional(nc->dev, NULL, 2, GPIOD_IN); in atmel_nand_controller_legacy_add_nands()
1835 if (IS_ERR(gpio)) { in atmel_nand_controller_legacy_add_nands()
1837 "Failed to get detect gpio (err = %ld)\n", in atmel_nand_controller_legacy_add_nands()
1838 PTR_ERR(gpio)); in atmel_nand_controller_legacy_add_nands()
1839 return PTR_ERR(gpio); in atmel_nand_controller_legacy_add_nands()
1842 nand->cdgpio = gpio; in atmel_nand_controller_legacy_add_nands()
1844 nand_set_flash_node(&nand->base, nc->dev->of_node); in atmel_nand_controller_legacy_add_nands()
1852 struct device *dev = nc->dev; in atmel_nand_controller_add_nands()
1857 if (nc->caps->legacy_of_bindings) in atmel_nand_controller_add_nands()
1860 np = dev->of_node; in atmel_nand_controller_add_nands()
1862 ret = of_property_read_u32(np, "#address-cells", &val); in atmel_nand_controller_add_nands()
1864 dev_err(dev, "missing #address-cells property\n"); in atmel_nand_controller_add_nands()
1870 ret = of_property_read_u32(np, "#size-cells", &val); in atmel_nand_controller_add_nands()
1872 dev_err(dev, "missing #size-cells property\n"); in atmel_nand_controller_add_nands()
1902 if (nc->dmac) in atmel_nand_controller_cleanup()
1903 dma_release_channel(nc->dmac); in atmel_nand_controller_cleanup()
1905 clk_put(nc->mck); in atmel_nand_controller_cleanup()
1943 .compatible = "atmel,at91sam9260-matrix",
1947 .compatible = "atmel,at91sam9261-matrix",
1951 .compatible = "atmel,at91sam9263-matrix",
1955 .compatible = "atmel,at91sam9rl-matrix",
1959 .compatible = "atmel,at91sam9g45-matrix",
1963 .compatible = "atmel,at91sam9n12-matrix",
1967 .compatible = "atmel,at91sam9x5-matrix",
1971 .compatible = "microchip,sam9x60-sfr",
1979 struct atmel_nand_controller *nc = to_nand_controller(chip->controller); in atmel_nand_attach_chip()
1984 ret = nc->caps->ops->ecc_init(chip); in atmel_nand_attach_chip()
1988 if (nc->caps->legacy_of_bindings || !nc->dev->of_node) { in atmel_nand_attach_chip()
1994 mtd->name = "atmel_nand"; in atmel_nand_attach_chip()
1995 } else if (!mtd->name) { in atmel_nand_attach_chip()
2003 * This way, mtd->name will be set by the core when in atmel_nand_attach_chip()
2006 mtd->name = devm_kasprintf(nc->dev, GFP_KERNEL, in atmel_nand_attach_chip()
2007 "%s:nand.%d", dev_name(nc->dev), in atmel_nand_attach_chip()
2008 nand->cs[0].id); in atmel_nand_attach_chip()
2009 if (!mtd->name) { in atmel_nand_attach_chip()
2010 dev_err(nc->dev, "Failed to allocate mtd->name\n"); in atmel_nand_attach_chip()
2011 return -ENOMEM; in atmel_nand_attach_chip()
2028 struct device *dev = &pdev->dev; in atmel_nand_controller_init()
2029 struct device_node *np = dev->of_node; in atmel_nand_controller_init()
2032 nand_controller_init(&nc->base); in atmel_nand_controller_init()
2033 nc->base.ops = &atmel_nand_controller_ops; in atmel_nand_controller_init()
2034 INIT_LIST_HEAD(&nc->chips); in atmel_nand_controller_init()
2035 nc->dev = dev; in atmel_nand_controller_init()
2036 nc->caps = caps; in atmel_nand_controller_init()
2040 nc->pmecc = devm_atmel_pmecc_get(dev); in atmel_nand_controller_init()
2041 if (IS_ERR(nc->pmecc)) in atmel_nand_controller_init()
2042 return dev_err_probe(dev, PTR_ERR(nc->pmecc), in atmel_nand_controller_init()
2045 if (nc->caps->has_dma && !atmel_nand_avoid_dma) { in atmel_nand_controller_init()
2051 nc->dmac = dma_request_channel(mask, NULL, NULL); in atmel_nand_controller_init()
2052 if (nc->dmac) in atmel_nand_controller_init()
2053 dev_info(nc->dev, "using %s for DMA transfers\n", in atmel_nand_controller_init()
2054 dma_chan_name(nc->dmac)); in atmel_nand_controller_init()
2056 dev_err(nc->dev, "Failed to request DMA channel\n"); in atmel_nand_controller_init()
2060 if (nc->caps->legacy_of_bindings) in atmel_nand_controller_init()
2063 nc->mck = of_clk_get(dev->parent->of_node, 0); in atmel_nand_controller_init()
2064 if (IS_ERR(nc->mck)) { in atmel_nand_controller_init()
2066 ret = PTR_ERR(nc->mck); in atmel_nand_controller_init()
2070 np = of_parse_phandle(dev->parent->of_node, "atmel,smc", 0); in atmel_nand_controller_init()
2073 ret = -EINVAL; in atmel_nand_controller_init()
2077 nc->smc = syscon_node_to_regmap(np); in atmel_nand_controller_init()
2079 if (IS_ERR(nc->smc)) { in atmel_nand_controller_init()
2080 ret = PTR_ERR(nc->smc); in atmel_nand_controller_init()
2088 if (nc->dmac) in atmel_nand_controller_init()
2089 dma_release_channel(nc->dmac); in atmel_nand_controller_init()
2097 struct device *dev = nc->base.dev; in atmel_smc_nand_controller_init()
2103 if (nc->base.caps->legacy_of_bindings) in atmel_smc_nand_controller_init()
2106 np = of_parse_phandle(dev->parent->of_node, in atmel_smc_nand_controller_init()
2107 nc->base.caps->ebi_csa_regmap_name, 0); in atmel_smc_nand_controller_init()
2117 nc->ebi_csa_regmap = syscon_node_to_regmap(np); in atmel_smc_nand_controller_init()
2119 if (IS_ERR(nc->ebi_csa_regmap)) { in atmel_smc_nand_controller_init()
2120 ret = PTR_ERR(nc->ebi_csa_regmap); in atmel_smc_nand_controller_init()
2125 nc->ebi_csa = (struct atmel_smc_nand_ebi_csa_cfg *)match->data; in atmel_smc_nand_controller_init()
2129 * add 4 to ->ebi_csa->offs. in atmel_smc_nand_controller_init()
2131 if (of_device_is_compatible(dev->parent->of_node, in atmel_smc_nand_controller_init()
2132 "atmel,at91sam9263-ebi1")) in atmel_smc_nand_controller_init()
2133 nc->ebi_csa->offs += 4; in atmel_smc_nand_controller_init()
2147 struct device *dev = nc->base.dev; in atmel_hsmc_nand_controller_legacy_init()
2153 nand_np = dev->of_node; in atmel_hsmc_nand_controller_legacy_init()
2154 nfc_np = of_get_compatible_child(dev->of_node, "atmel,sama5d3-nfc"); in atmel_hsmc_nand_controller_legacy_init()
2156 dev_err(dev, "Could not find device node for sama5d3-nfc\n"); in atmel_hsmc_nand_controller_legacy_init()
2157 return -ENODEV; in atmel_hsmc_nand_controller_legacy_init()
2160 nc->clk = of_clk_get(nfc_np, 0); in atmel_hsmc_nand_controller_legacy_init()
2161 if (IS_ERR(nc->clk)) { in atmel_hsmc_nand_controller_legacy_init()
2162 ret = PTR_ERR(nc->clk); in atmel_hsmc_nand_controller_legacy_init()
2168 ret = clk_prepare_enable(nc->clk); in atmel_hsmc_nand_controller_legacy_init()
2175 nc->irq = of_irq_get(nand_np, 0); in atmel_hsmc_nand_controller_legacy_init()
2176 if (nc->irq <= 0) { in atmel_hsmc_nand_controller_legacy_init()
2177 ret = nc->irq ?: -ENXIO; in atmel_hsmc_nand_controller_legacy_init()
2178 if (ret != -EPROBE_DEFER) in atmel_hsmc_nand_controller_legacy_init()
2197 regmap_conf.name = "nfc-io"; in atmel_hsmc_nand_controller_legacy_init()
2198 regmap_conf.max_register = resource_size(&res) - 4; in atmel_hsmc_nand_controller_legacy_init()
2199 nc->io = devm_regmap_init_mmio(dev, iomem, ®map_conf); in atmel_hsmc_nand_controller_legacy_init()
2200 if (IS_ERR(nc->io)) { in atmel_hsmc_nand_controller_legacy_init()
2201 ret = PTR_ERR(nc->io); in atmel_hsmc_nand_controller_legacy_init()
2221 regmap_conf.max_register = resource_size(&res) - 4; in atmel_hsmc_nand_controller_legacy_init()
2222 nc->base.smc = devm_regmap_init_mmio(dev, iomem, ®map_conf); in atmel_hsmc_nand_controller_legacy_init()
2223 if (IS_ERR(nc->base.smc)) { in atmel_hsmc_nand_controller_legacy_init()
2224 ret = PTR_ERR(nc->base.smc); in atmel_hsmc_nand_controller_legacy_init()
2237 nc->sram.virt = devm_ioremap_resource(dev, &res); in atmel_hsmc_nand_controller_legacy_init()
2238 if (IS_ERR(nc->sram.virt)) { in atmel_hsmc_nand_controller_legacy_init()
2239 ret = PTR_ERR(nc->sram.virt); in atmel_hsmc_nand_controller_legacy_init()
2243 nc->sram.dma = res.start; in atmel_hsmc_nand_controller_legacy_init()
2254 struct device *dev = nc->base.dev; in atmel_hsmc_nand_controller_init()
2258 np = of_parse_phandle(dev->parent->of_node, "atmel,smc", 0); in atmel_hsmc_nand_controller_init()
2261 return -EINVAL; in atmel_hsmc_nand_controller_init()
2264 nc->hsmc_layout = atmel_hsmc_get_reg_layout(np); in atmel_hsmc_nand_controller_init()
2266 nc->irq = of_irq_get(np, 0); in atmel_hsmc_nand_controller_init()
2268 if (nc->irq <= 0) { in atmel_hsmc_nand_controller_init()
2269 ret = nc->irq ?: -ENXIO; in atmel_hsmc_nand_controller_init()
2270 if (ret != -EPROBE_DEFER) in atmel_hsmc_nand_controller_init()
2276 np = of_parse_phandle(dev->of_node, "atmel,nfc-io", 0); in atmel_hsmc_nand_controller_init()
2278 dev_err(dev, "Missing or invalid atmel,nfc-io property\n"); in atmel_hsmc_nand_controller_init()
2279 return -EINVAL; in atmel_hsmc_nand_controller_init()
2282 nc->io = syscon_node_to_regmap(np); in atmel_hsmc_nand_controller_init()
2284 if (IS_ERR(nc->io)) { in atmel_hsmc_nand_controller_init()
2285 ret = PTR_ERR(nc->io); in atmel_hsmc_nand_controller_init()
2290 nc->sram.pool = of_gen_pool_get(nc->base.dev->of_node, in atmel_hsmc_nand_controller_init()
2291 "atmel,nfc-sram", 0); in atmel_hsmc_nand_controller_init()
2292 if (!nc->sram.pool) { in atmel_hsmc_nand_controller_init()
2293 dev_err(nc->base.dev, "Missing SRAM\n"); in atmel_hsmc_nand_controller_init()
2294 return -ENOMEM; in atmel_hsmc_nand_controller_init()
2297 nc->sram.virt = (void __iomem *)gen_pool_dma_alloc(nc->sram.pool, in atmel_hsmc_nand_controller_init()
2299 &nc->sram.dma); in atmel_hsmc_nand_controller_init()
2300 if (!nc->sram.virt) { in atmel_hsmc_nand_controller_init()
2301 dev_err(nc->base.dev, in atmel_hsmc_nand_controller_init()
2303 return -ENOMEM; in atmel_hsmc_nand_controller_init()
2320 regmap_write(hsmc_nc->base.smc, ATMEL_HSMC_NFC_CTRL, in atmel_hsmc_nand_controller_remove()
2323 if (hsmc_nc->sram.pool) in atmel_hsmc_nand_controller_remove()
2324 gen_pool_free(hsmc_nc->sram.pool, in atmel_hsmc_nand_controller_remove()
2325 (unsigned long)hsmc_nc->sram.virt, in atmel_hsmc_nand_controller_remove()
2328 if (hsmc_nc->clk) { in atmel_hsmc_nand_controller_remove()
2329 clk_disable_unprepare(hsmc_nc->clk); in atmel_hsmc_nand_controller_remove()
2330 clk_put(hsmc_nc->clk); in atmel_hsmc_nand_controller_remove()
2341 struct device *dev = &pdev->dev; in atmel_hsmc_nand_controller_probe()
2347 return -ENOMEM; in atmel_hsmc_nand_controller_probe()
2349 ret = atmel_nand_controller_init(&nc->base, pdev, caps); in atmel_hsmc_nand_controller_probe()
2353 if (caps->legacy_of_bindings) in atmel_hsmc_nand_controller_probe()
2362 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff); in atmel_hsmc_nand_controller_probe()
2363 ret = devm_request_irq(dev, nc->irq, atmel_nfc_interrupt, in atmel_hsmc_nand_controller_probe()
2373 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CFG, in atmel_hsmc_nand_controller_probe()
2375 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL, in atmel_hsmc_nand_controller_probe()
2378 ret = atmel_nand_controller_add_nands(&nc->base); in atmel_hsmc_nand_controller_probe()
2385 atmel_hsmc_nand_controller_remove(&nc->base); in atmel_hsmc_nand_controller_probe()
2418 struct device *dev = &pdev->dev; in atmel_smc_nand_controller_probe()
2424 return -ENOMEM; in atmel_smc_nand_controller_probe()
2426 ret = atmel_nand_controller_init(&nc->base, pdev, caps); in atmel_smc_nand_controller_probe()
2434 return atmel_nand_controller_add_nands(&nc->base); in atmel_smc_nand_controller_probe()
2453 * from re-using atmel_smc_nand_setup_interface() for the
2454 * ->setup_interface() hook.
2456 * ->setup_interface() unassigned.
2537 .compatible = "atmel,at91rm9200-nand-controller",
2541 .compatible = "atmel,at91sam9260-nand-controller",
2545 .compatible = "atmel,at91sam9261-nand-controller",
2549 .compatible = "atmel,at91sam9g45-nand-controller",
2553 .compatible = "atmel,sama5d3-nand-controller",
2557 .compatible = "microchip,sam9x60-nand-controller",
2562 .compatible = "atmel,at91rm9200-nand",
2566 .compatible = "atmel,sama5d4-nand",
2570 .compatible = "atmel,sama5d2-nand",
2581 if (pdev->id_entry) in atmel_nand_controller_probe()
2582 caps = (void *)pdev->id_entry->driver_data; in atmel_nand_controller_probe()
2584 caps = of_device_get_match_data(&pdev->dev); in atmel_nand_controller_probe()
2587 dev_err(&pdev->dev, "Could not retrieve NFC caps\n"); in atmel_nand_controller_probe()
2588 return -EINVAL; in atmel_nand_controller_probe()
2591 if (caps->legacy_of_bindings) { in atmel_nand_controller_probe()
2599 nfc_node = of_get_compatible_child(pdev->dev.of_node, in atmel_nand_controller_probe()
2600 "atmel,sama5d3-nfc"); in atmel_nand_controller_probe()
2608 * at91rm9200 controller, the atmel,nand-has-dma specify that in atmel_nand_controller_probe()
2612 if (!caps->has_dma && in atmel_nand_controller_probe()
2613 of_property_read_bool(pdev->dev.of_node, in atmel_nand_controller_probe()
2614 "atmel,nand-has-dma")) in atmel_nand_controller_probe()
2619 * CLE to A22. If atmel,nand-addr-offset != 21 this means we're in atmel_nand_controller_probe()
2622 of_property_read_u32(pdev->dev.of_node, in atmel_nand_controller_probe()
2623 "atmel,nand-addr-offset", &ale_offs); in atmel_nand_controller_probe()
2628 return caps->ops->probe(pdev, caps); in atmel_nand_controller_probe()
2635 WARN_ON(nc->caps->ops->remove(nc)); in atmel_nand_controller_remove()
2643 if (nc->pmecc) in atmel_nand_controller_resume()
2644 atmel_pmecc_reset(nc->pmecc); in atmel_nand_controller_resume()
2646 list_for_each_entry(nand, &nc->chips, node) { in atmel_nand_controller_resume()
2649 for (i = 0; i < nand->numcs; i++) in atmel_nand_controller_resume()
2650 nand_reset(&nand->base, i); in atmel_nand_controller_resume()
2661 .name = "atmel-nand-controller",
2671 MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
2673 MODULE_ALIAS("platform:atmel-nand-controller");