30 #define AMD_WINDOW_MAXSIZE	0x00200000
36 #define SC520_PAR_ADDR_MASK	0x00003fff
41 #define SC520_PAR_SIZE_MASK	0x01ffc000
51 #define SC520_PAR_BOOTCS	0x8a000000
52 #define	SC520_PAR_ROMCS1	0xaa000000
53 #define SC520_PAR_ROMCS2	0xca000000	/* Cache disabled, 64K page */
69 	.size = 0,
76 		.offset = 0,
77 		.size = 0x000e0000
81 		.offset = 0x00100000,
85 		.offset = 0x000e0000,
86 		.size = 0x00020000
90 		.offset = 0
94 		.offset = 0x007e0000,
95 		.size = 0x00020000
99 		.offset = 0x007e0000,
100 		.size = 0x00020000
114 		.offset = 0x000e0000,
115 		.size = 0x00010000
119 		.offset = 0x000f0000,
120 		.size = 0x00010000
124 		.offset = 0
128 		.offset = 0x001f0000,
129 		.size = 0x00010000
149 	for (b = 0; (b < nettel_intel_partitions[3].size); b += 0x100000) {  in nettel_reboot_notifier()
150 		cfi_send_gen_cmd(0xff, 0x55, b, &nettel_intel_map, cfi,  in nettel_reboot_notifier()
157 	nettel_reboot_notifier, NULL, 0
168 	int num_amd_partitions=0;  in nettel_init()
177 	int rc = 0;  in nettel_init()
179 	nettel_mmcrp = (void *) ioremap(0xfffef000, 4096);  in nettel_init()
186 	*((unsigned char *) (nettel_mmcrp + 0xc64)) = 0x01;  in nettel_init()
188 	amdpar = (volatile unsigned long *) (nettel_mmcrp + 0xc4);  in nettel_init()
191 	intelboot = 0;  in nettel_init()
193 	intel0par = (volatile unsigned long *) (nettel_mmcrp + 0xc0);  in nettel_init()
195 	intel1par = (volatile unsigned long *) (nettel_mmcrp + 0xbc);  in nettel_init()
203 	*intel0par = 0;  in nettel_init()
204 	*intel1par = 0;  in nettel_init()
213 	amdaddr = 0x20000000;  in nettel_init()
258 				(nettel_mmcrp + 0xc4);  in nettel_init()
261 				(nettel_mmcrp + 0xc0);  in nettel_init()
269 				(nettel_mmcrp + 0xc0);  in nettel_init()
272 				(nettel_mmcrp + 0xc4);  in nettel_init()
301 	*intel1par = 0;  in nettel_init()
354 	if (intel1size > 0) {  in nettel_init()
358 		*intel1par = 0;  in nettel_init()