76 	int bus_width;  member
94 static inline u_int build_mr_cfgmask(u_int bus_width)  in build_mr_cfgmask()  argument
98 	if (bus_width == 0x0004)		/* x32 device */  in build_mr_cfgmask()
107 static inline u_int build_sr_ok_datamask(u_int bus_width)  in build_sr_ok_datamask()  argument
111 	if (bus_width == 0x0004)		/* x32 device */  in build_sr_ok_datamask()
125 	val = map->pfow_base + offset*pcm_data->bus_width;  in ow_reg_add()
140 	writel_relaxed(build_mr_cfgmask(pcm_data->bus_width) | 0x18,  in ow_enable()
155 	writel_relaxed(build_mr_cfgmask(pcm_data->bus_width) | 0x18,  in ow_disable()
172 	u_int sr_ok_datamask = build_sr_ok_datamask(pcm_data->bus_width);  in lpddr2_nvm_do_op()
191 	if (pcm_data->bus_width == 0x0004) {	/* 2x16 devices stacked */  in lpddr2_nvm_do_op()
213 	if (pcm_data->bus_width == 0x0004)	/* 2x16 devices stacked */  in lpddr2_nvm_do_op()
220 		if (pcm_data->bus_width == 0x0004) {/* 2x16 devices stacked */  in lpddr2_nvm_do_op()
338 			if (pcm_data->bus_width == 0x0004) {/* 2x16 devices */  in lpddr2_nvm_write()
347 			add += pcm_data->bus_width;  in lpddr2_nvm_write()
348 			tot_len += pcm_data->bus_width;  in lpddr2_nvm_write()
422 	pcm_data->bus_width = BUS_WIDTH;  in lpddr2_nvm_probe()
444 		.bankwidth	= pcm_data->bus_width / 2,  in lpddr2_nvm_probe()
464 	mtd->erasesize		= ERASE_BLOCKSIZE * pcm_data->bus_width;  in lpddr2_nvm_probe()
465 	mtd->writebufsize	= WRITE_BUFFSIZE * pcm_data->bus_width;  in lpddr2_nvm_probe()