51 #define SMI_CR1		0x0	/* SMI control register 1 */  macro
229 	ctrlreg1 = readl(dev->io_base + SMI_CR1);  in spear_smi_read_sr()
231 	writel(ctrlreg1 & ~(SW_MODE | WB_MODE), dev->io_base + SMI_CR1);  in spear_smi_read_sr()
248 	writel(ctrlreg1, dev->io_base + SMI_CR1);  in spear_smi_read_sr()
345 	writel(val, dev->io_base + SMI_CR1);  in spear_smi_hw_init()
387 	ctrlreg1 = readl(dev->io_base + SMI_CR1);  in spear_smi_write_enable()
389 	writel(ctrlreg1 & ~SW_MODE, dev->io_base + SMI_CR1);  in spear_smi_write_enable()
398 	writel(ctrlreg1, dev->io_base + SMI_CR1);  in spear_smi_write_enable()
460 	ctrlreg1 = readl(dev->io_base + SMI_CR1);  in spear_smi_erase_sector()
461 	writel((ctrlreg1 | SW_MODE) & ~WB_MODE, dev->io_base + SMI_CR1);  in spear_smi_erase_sector()
479 	writel(ctrlreg1, dev->io_base + SMI_CR1);  in spear_smi_erase_sector()
576 	ctrlreg1 = val = readl(dev->io_base + SMI_CR1);  in spear_mtd_read()
581 	writel(val, dev->io_base + SMI_CR1);  in spear_mtd_read()
586 	writel(ctrlreg1, dev->io_base + SMI_CR1);  in spear_mtd_read()
634 	ctrlreg1 = readl(dev->io_base + SMI_CR1);  in spear_smi_cpy_toio()
635 	writel((ctrlreg1 | WB_MODE) & ~SW_MODE, dev->io_base + SMI_CR1);  in spear_smi_cpy_toio()
655 	writel(ctrlreg1, dev->io_base + SMI_CR1);  in spear_smi_cpy_toio()
758 	val = readl(dev->io_base + SMI_CR1);  in spear_smi_probe_flash()
759 	writel(val | SW_MODE, dev->io_base + SMI_CR1);  in spear_smi_probe_flash()
783 	val = readl(dev->io_base + SMI_CR1);  in spear_smi_probe_flash()
784 	writel(val & ~SW_MODE, dev->io_base + SMI_CR1);  in spear_smi_probe_flash()