Lines Matching refs:SPMMC_SD_CONFIG0_REG
74 #define SPMMC_SD_CONFIG0_REG 0x0090 macro
236 u32 value = readl(host->base + SPMMC_SD_CONFIG0_REG); in spmmc_set_bus_clk()
248 writel(value, host->base + SPMMC_SD_CONFIG0_REG); in spmmc_set_bus_clk()
254 int clkdiv = FIELD_GET(SPMMC_CLOCK_DIVISION, readl(host->base + SPMMC_SD_CONFIG0_REG)); in spmmc_set_bus_timing()
294 value = readl(host->base + SPMMC_SD_CONFIG0_REG); in spmmc_set_bus_timing()
296 writel(value, host->base + SPMMC_SD_CONFIG0_REG); in spmmc_set_bus_timing()
298 value = readl(host->base + SPMMC_SD_CONFIG0_REG); in spmmc_set_bus_timing()
300 writel(value, host->base + SPMMC_SD_CONFIG0_REG); in spmmc_set_bus_timing()
306 u32 value = readl(host->base + SPMMC_SD_CONFIG0_REG); in spmmc_set_bus_width()
322 writel(value, host->base + SPMMC_SD_CONFIG0_REG); in spmmc_set_bus_width()
330 u32 value = readl(host->base + SPMMC_SD_CONFIG0_REG); in spmmc_set_sdmmc_mode()
334 writel(value, host->base + SPMMC_SD_CONFIG0_REG); in spmmc_set_sdmmc_mode()
374 value = readl(host->base + SPMMC_SD_CONFIG0_REG); in spmmc_prepare_cmd()
381 writel(value, host->base + SPMMC_SD_CONFIG0_REG); in spmmc_prepare_cmd()
398 writel(value, host->base + SPMMC_SD_CONFIG0_REG); in spmmc_prepare_cmd()
407 value = readl(host->base + SPMMC_SD_CONFIG0_REG); in spmmc_prepare_data()
474 writel(value, host->base + SPMMC_SD_CONFIG0_REG); in spmmc_prepare_data()
486 writel(value, host->base + SPMMC_SD_CONFIG0_REG); in spmmc_prepare_data()