Lines Matching full:host
43 #include <linux/mmc/host.h>
255 #define sh_mmcif_host_to_dev(host) (&host->pd->dev) argument
257 static inline void sh_mmcif_bitset(struct sh_mmcif_host *host, in sh_mmcif_bitset() argument
260 writel(val | readl(host->addr + reg), host->addr + reg); in sh_mmcif_bitset()
263 static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host, in sh_mmcif_bitclr() argument
266 writel(~val & readl(host->addr + reg), host->addr + reg); in sh_mmcif_bitclr()
271 struct sh_mmcif_host *host = arg; in sh_mmcif_dma_complete() local
272 struct mmc_request *mrq = host->mrq; in sh_mmcif_dma_complete()
273 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_dma_complete()
281 complete(&host->dma_complete); in sh_mmcif_dma_complete()
284 static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host) in sh_mmcif_start_dma_rx() argument
286 struct mmc_data *data = host->mrq->data; in sh_mmcif_start_dma_rx()
289 struct dma_chan *chan = host->chan_rx; in sh_mmcif_start_dma_rx()
290 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_start_dma_rx()
297 host->dma_active = true; in sh_mmcif_start_dma_rx()
304 desc->callback_param = host; in sh_mmcif_start_dma_rx()
306 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN); in sh_mmcif_start_dma_rx()
316 host->chan_rx = NULL; in sh_mmcif_start_dma_rx()
317 host->dma_active = false; in sh_mmcif_start_dma_rx()
320 chan = host->chan_tx; in sh_mmcif_start_dma_rx()
322 host->chan_tx = NULL; in sh_mmcif_start_dma_rx()
327 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); in sh_mmcif_start_dma_rx()
334 static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host) in sh_mmcif_start_dma_tx() argument
336 struct mmc_data *data = host->mrq->data; in sh_mmcif_start_dma_tx()
339 struct dma_chan *chan = host->chan_tx; in sh_mmcif_start_dma_tx()
340 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_start_dma_tx()
347 host->dma_active = true; in sh_mmcif_start_dma_tx()
354 desc->callback_param = host; in sh_mmcif_start_dma_tx()
356 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN); in sh_mmcif_start_dma_tx()
366 host->chan_tx = NULL; in sh_mmcif_start_dma_tx()
367 host->dma_active = false; in sh_mmcif_start_dma_tx()
370 chan = host->chan_rx; in sh_mmcif_start_dma_tx()
372 host->chan_rx = NULL; in sh_mmcif_start_dma_tx()
377 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); in sh_mmcif_start_dma_tx()
385 sh_mmcif_request_dma_pdata(struct sh_mmcif_host *host, uintptr_t slave_id) in sh_mmcif_request_dma_pdata() argument
397 static int sh_mmcif_dma_slave_config(struct sh_mmcif_host *host, in sh_mmcif_dma_slave_config() argument
404 res = platform_get_resource(host->pd, IORESOURCE_MEM, 0); in sh_mmcif_dma_slave_config()
421 static void sh_mmcif_request_dma(struct sh_mmcif_host *host) in sh_mmcif_request_dma() argument
423 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_request_dma()
424 host->dma_active = false; in sh_mmcif_request_dma()
430 host->chan_tx = sh_mmcif_request_dma_pdata(host, in sh_mmcif_request_dma()
432 host->chan_rx = sh_mmcif_request_dma_pdata(host, in sh_mmcif_request_dma()
435 host->chan_tx = dma_request_chan(dev, "tx"); in sh_mmcif_request_dma()
436 if (IS_ERR(host->chan_tx)) in sh_mmcif_request_dma()
437 host->chan_tx = NULL; in sh_mmcif_request_dma()
438 host->chan_rx = dma_request_chan(dev, "rx"); in sh_mmcif_request_dma()
439 if (IS_ERR(host->chan_rx)) in sh_mmcif_request_dma()
440 host->chan_rx = NULL; in sh_mmcif_request_dma()
442 dev_dbg(dev, "%s: got channel TX %p RX %p\n", __func__, host->chan_tx, in sh_mmcif_request_dma()
443 host->chan_rx); in sh_mmcif_request_dma()
445 if (!host->chan_tx || !host->chan_rx || in sh_mmcif_request_dma()
446 sh_mmcif_dma_slave_config(host, host->chan_tx, DMA_MEM_TO_DEV) || in sh_mmcif_request_dma()
447 sh_mmcif_dma_slave_config(host, host->chan_rx, DMA_DEV_TO_MEM)) in sh_mmcif_request_dma()
453 if (host->chan_tx) in sh_mmcif_request_dma()
454 dma_release_channel(host->chan_tx); in sh_mmcif_request_dma()
455 if (host->chan_rx) in sh_mmcif_request_dma()
456 dma_release_channel(host->chan_rx); in sh_mmcif_request_dma()
457 host->chan_tx = host->chan_rx = NULL; in sh_mmcif_request_dma()
460 static void sh_mmcif_release_dma(struct sh_mmcif_host *host) in sh_mmcif_release_dma() argument
462 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); in sh_mmcif_release_dma()
464 if (host->chan_tx) { in sh_mmcif_release_dma()
465 struct dma_chan *chan = host->chan_tx; in sh_mmcif_release_dma()
466 host->chan_tx = NULL; in sh_mmcif_release_dma()
469 if (host->chan_rx) { in sh_mmcif_release_dma()
470 struct dma_chan *chan = host->chan_rx; in sh_mmcif_release_dma()
471 host->chan_rx = NULL; in sh_mmcif_release_dma()
475 host->dma_active = false; in sh_mmcif_release_dma()
478 static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk) in sh_mmcif_clock_control() argument
480 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_clock_control()
483 unsigned int current_clk = clk_get_rate(host->clk); in sh_mmcif_clock_control()
486 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); in sh_mmcif_clock_control()
487 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR); in sh_mmcif_clock_control()
492 if (host->clkdiv_map) { in sh_mmcif_clock_control()
500 if (!((1 << i) & host->clkdiv_map)) in sh_mmcif_clock_control()
509 freq = clk_round_rate(host->clk, clk * div); in sh_mmcif_clock_control()
523 clk_set_rate(host->clk, best_freq); in sh_mmcif_clock_control()
531 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR & clkdiv); in sh_mmcif_clock_control()
532 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); in sh_mmcif_clock_control()
535 static void sh_mmcif_sync_reset(struct sh_mmcif_host *host) in sh_mmcif_sync_reset() argument
539 tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL); in sh_mmcif_sync_reset()
541 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON); in sh_mmcif_sync_reset()
542 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF); in sh_mmcif_sync_reset()
543 if (host->ccs_enable) in sh_mmcif_sync_reset()
545 if (host->clk_ctrl2_enable) in sh_mmcif_sync_reset()
546 sh_mmcif_writel(host->addr, MMCIF_CE_CLK_CTRL2, 0x0F0F0000); in sh_mmcif_sync_reset()
547 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp | in sh_mmcif_sync_reset()
550 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP); in sh_mmcif_sync_reset()
553 static int sh_mmcif_error_manage(struct sh_mmcif_host *host) in sh_mmcif_error_manage() argument
555 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_error_manage()
559 host->sd_error = false; in sh_mmcif_error_manage()
561 state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1); in sh_mmcif_error_manage()
562 state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2); in sh_mmcif_error_manage()
567 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK); in sh_mmcif_error_manage()
568 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK); in sh_mmcif_error_manage()
570 if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1) in sh_mmcif_error_manage()
580 sh_mmcif_sync_reset(host); in sh_mmcif_error_manage()
587 host->state, host->wait_for); in sh_mmcif_error_manage()
591 host->state, host->wait_for); in sh_mmcif_error_manage()
595 host->state, host->wait_for); in sh_mmcif_error_manage()
601 static void sh_mmcif_single_read(struct sh_mmcif_host *host, in sh_mmcif_single_read() argument
606 host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & in sh_mmcif_single_read()
609 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, in sh_mmcif_single_read()
612 host->wait_for = MMCIF_WAIT_FOR_READ; in sh_mmcif_single_read()
615 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); in sh_mmcif_single_read()
618 static bool sh_mmcif_read_block(struct sh_mmcif_host *host) in sh_mmcif_read_block() argument
620 struct sg_mapping_iter *sgm = &host->sg_miter; in sh_mmcif_read_block()
621 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_read_block()
622 struct mmc_data *data = host->mrq->data; in sh_mmcif_read_block()
626 if (host->sd_error) { in sh_mmcif_read_block()
628 data->error = sh_mmcif_error_manage(host); in sh_mmcif_read_block()
641 for (i = 0; i < host->blocksize / 4; i++) in sh_mmcif_read_block()
642 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); in sh_mmcif_read_block()
644 sg_miter_stop(&host->sg_miter); in sh_mmcif_read_block()
647 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); in sh_mmcif_read_block()
648 host->wait_for = MMCIF_WAIT_FOR_READ_END; in sh_mmcif_read_block()
653 static void sh_mmcif_multi_read(struct sh_mmcif_host *host, in sh_mmcif_multi_read() argument
656 struct sg_mapping_iter *sgm = &host->sg_miter; in sh_mmcif_multi_read()
662 host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & in sh_mmcif_multi_read()
674 host->wait_for = MMCIF_WAIT_FOR_MREAD; in sh_mmcif_multi_read()
676 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); in sh_mmcif_multi_read()
679 static bool sh_mmcif_mread_block(struct sh_mmcif_host *host) in sh_mmcif_mread_block() argument
681 struct sg_mapping_iter *sgm = &host->sg_miter; in sh_mmcif_mread_block()
682 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_mread_block()
683 struct mmc_data *data = host->mrq->data; in sh_mmcif_mread_block()
687 if (host->sd_error) { in sh_mmcif_mread_block()
689 data->error = sh_mmcif_error_manage(host); in sh_mmcif_mread_block()
696 for (i = 0; i < host->blocksize / 4; i++) in sh_mmcif_mread_block()
697 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); in sh_mmcif_mread_block()
699 sgm->consumed = host->blocksize; in sh_mmcif_mread_block()
701 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); in sh_mmcif_mread_block()
711 static void sh_mmcif_single_write(struct sh_mmcif_host *host, in sh_mmcif_single_write() argument
716 host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & in sh_mmcif_single_write()
719 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, in sh_mmcif_single_write()
722 host->wait_for = MMCIF_WAIT_FOR_WRITE; in sh_mmcif_single_write()
725 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); in sh_mmcif_single_write()
728 static bool sh_mmcif_write_block(struct sh_mmcif_host *host) in sh_mmcif_write_block() argument
730 struct sg_mapping_iter *sgm = &host->sg_miter; in sh_mmcif_write_block()
731 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_write_block()
732 struct mmc_data *data = host->mrq->data; in sh_mmcif_write_block()
736 if (host->sd_error) { in sh_mmcif_write_block()
738 data->error = sh_mmcif_error_manage(host); in sh_mmcif_write_block()
751 for (i = 0; i < host->blocksize / 4; i++) in sh_mmcif_write_block()
752 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); in sh_mmcif_write_block()
754 sg_miter_stop(&host->sg_miter); in sh_mmcif_write_block()
757 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); in sh_mmcif_write_block()
758 host->wait_for = MMCIF_WAIT_FOR_WRITE_END; in sh_mmcif_write_block()
763 static void sh_mmcif_multi_write(struct sh_mmcif_host *host, in sh_mmcif_multi_write() argument
766 struct sg_mapping_iter *sgm = &host->sg_miter; in sh_mmcif_multi_write()
772 host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & in sh_mmcif_multi_write()
784 host->wait_for = MMCIF_WAIT_FOR_MWRITE; in sh_mmcif_multi_write()
786 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); in sh_mmcif_multi_write()
789 static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host) in sh_mmcif_mwrite_block() argument
791 struct sg_mapping_iter *sgm = &host->sg_miter; in sh_mmcif_mwrite_block()
792 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_mwrite_block()
793 struct mmc_data *data = host->mrq->data; in sh_mmcif_mwrite_block()
797 if (host->sd_error) { in sh_mmcif_mwrite_block()
799 data->error = sh_mmcif_error_manage(host); in sh_mmcif_mwrite_block()
806 for (i = 0; i < host->blocksize / 4; i++) in sh_mmcif_mwrite_block()
807 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); in sh_mmcif_mwrite_block()
809 sgm->consumed = host->blocksize; in sh_mmcif_mwrite_block()
816 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); in sh_mmcif_mwrite_block()
821 static void sh_mmcif_get_response(struct sh_mmcif_host *host, in sh_mmcif_get_response() argument
825 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3); in sh_mmcif_get_response()
826 cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2); in sh_mmcif_get_response()
827 cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1); in sh_mmcif_get_response()
828 cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); in sh_mmcif_get_response()
830 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); in sh_mmcif_get_response()
833 static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host, in sh_mmcif_get_cmd12response() argument
836 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12); in sh_mmcif_get_cmd12response()
839 static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host, in sh_mmcif_set_cmd() argument
842 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_set_cmd()
871 switch (host->bus_width) { in sh_mmcif_set_cmd()
885 switch (host->timing) { in sh_mmcif_set_cmd()
888 * MMC core will only set this timing, if the host in sh_mmcif_set_cmd()
904 sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET, in sh_mmcif_set_cmd()
922 static int sh_mmcif_data_trans(struct sh_mmcif_host *host, in sh_mmcif_data_trans() argument
925 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_data_trans()
929 sh_mmcif_multi_read(host, mrq); in sh_mmcif_data_trans()
932 sh_mmcif_multi_write(host, mrq); in sh_mmcif_data_trans()
935 sh_mmcif_single_write(host, mrq); in sh_mmcif_data_trans()
939 sh_mmcif_single_read(host, mrq); in sh_mmcif_data_trans()
947 static void sh_mmcif_start_cmd(struct sh_mmcif_host *host, in sh_mmcif_start_cmd() argument
960 if (host->ccs_enable) in sh_mmcif_start_cmd()
964 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0); in sh_mmcif_start_cmd()
965 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, in sh_mmcif_start_cmd()
968 opc = sh_mmcif_set_cmd(host, mrq); in sh_mmcif_start_cmd()
970 if (host->ccs_enable) in sh_mmcif_start_cmd()
971 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0); in sh_mmcif_start_cmd()
973 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0 | INT_CCS); in sh_mmcif_start_cmd()
974 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask); in sh_mmcif_start_cmd()
976 sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg); in sh_mmcif_start_cmd()
978 spin_lock_irqsave(&host->lock, flags); in sh_mmcif_start_cmd()
979 sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc); in sh_mmcif_start_cmd()
981 host->wait_for = MMCIF_WAIT_FOR_CMD; in sh_mmcif_start_cmd()
982 schedule_delayed_work(&host->timeout_work, host->timeout); in sh_mmcif_start_cmd()
983 spin_unlock_irqrestore(&host->lock, flags); in sh_mmcif_start_cmd()
986 static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host, in sh_mmcif_stop_cmd() argument
989 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_stop_cmd()
993 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); in sh_mmcif_stop_cmd()
996 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); in sh_mmcif_stop_cmd()
1000 mrq->stop->error = sh_mmcif_error_manage(host); in sh_mmcif_stop_cmd()
1004 host->wait_for = MMCIF_WAIT_FOR_STOP; in sh_mmcif_stop_cmd()
1009 struct sh_mmcif_host *host = mmc_priv(mmc); in sh_mmcif_request() local
1010 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_request()
1013 spin_lock_irqsave(&host->lock, flags); in sh_mmcif_request()
1014 if (host->state != STATE_IDLE) { in sh_mmcif_request()
1016 __func__, host->state); in sh_mmcif_request()
1017 spin_unlock_irqrestore(&host->lock, flags); in sh_mmcif_request()
1023 host->state = STATE_REQUEST; in sh_mmcif_request()
1024 spin_unlock_irqrestore(&host->lock, flags); in sh_mmcif_request()
1026 host->mrq = mrq; in sh_mmcif_request()
1028 sh_mmcif_start_cmd(host, mrq); in sh_mmcif_request()
1031 static void sh_mmcif_clk_setup(struct sh_mmcif_host *host) in sh_mmcif_clk_setup() argument
1033 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_clk_setup()
1035 if (host->mmc->f_max) { in sh_mmcif_clk_setup()
1038 f_max = host->mmc->f_max; in sh_mmcif_clk_setup()
1040 f_min = clk_round_rate(host->clk, f_min_old / 2); in sh_mmcif_clk_setup()
1049 host->clkdiv_map = 0x3ff; in sh_mmcif_clk_setup()
1051 host->mmc->f_max = f_max >> ffs(host->clkdiv_map); in sh_mmcif_clk_setup()
1052 host->mmc->f_min = f_min >> fls(host->clkdiv_map); in sh_mmcif_clk_setup()
1054 unsigned int clk = clk_get_rate(host->clk); in sh_mmcif_clk_setup()
1056 host->mmc->f_max = clk / 2; in sh_mmcif_clk_setup()
1057 host->mmc->f_min = clk / 512; in sh_mmcif_clk_setup()
1061 host->mmc->f_max, host->mmc->f_min); in sh_mmcif_clk_setup()
1066 struct sh_mmcif_host *host = mmc_priv(mmc); in sh_mmcif_set_ios() local
1067 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_set_ios()
1070 spin_lock_irqsave(&host->lock, flags); in sh_mmcif_set_ios()
1071 if (host->state != STATE_IDLE) { in sh_mmcif_set_ios()
1073 __func__, host->state); in sh_mmcif_set_ios()
1074 spin_unlock_irqrestore(&host->lock, flags); in sh_mmcif_set_ios()
1078 host->state = STATE_IOS; in sh_mmcif_set_ios()
1079 spin_unlock_irqrestore(&host->lock, flags); in sh_mmcif_set_ios()
1085 if (!host->power) { in sh_mmcif_set_ios()
1086 clk_prepare_enable(host->clk); in sh_mmcif_set_ios()
1088 sh_mmcif_sync_reset(host); in sh_mmcif_set_ios()
1089 sh_mmcif_request_dma(host); in sh_mmcif_set_ios()
1090 host->power = true; in sh_mmcif_set_ios()
1096 if (host->power) { in sh_mmcif_set_ios()
1097 sh_mmcif_clock_control(host, 0); in sh_mmcif_set_ios()
1098 sh_mmcif_release_dma(host); in sh_mmcif_set_ios()
1100 clk_disable_unprepare(host->clk); in sh_mmcif_set_ios()
1101 host->power = false; in sh_mmcif_set_ios()
1105 sh_mmcif_clock_control(host, ios->clock); in sh_mmcif_set_ios()
1109 host->timing = ios->timing; in sh_mmcif_set_ios()
1110 host->bus_width = ios->bus_width; in sh_mmcif_set_ios()
1111 host->state = STATE_IDLE; in sh_mmcif_set_ios()
1120 static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host) in sh_mmcif_end_cmd() argument
1122 struct mmc_command *cmd = host->mrq->cmd; in sh_mmcif_end_cmd()
1123 struct mmc_data *data = host->mrq->data; in sh_mmcif_end_cmd()
1124 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_end_cmd()
1127 if (host->sd_error) { in sh_mmcif_end_cmd()
1135 cmd->error = sh_mmcif_error_manage(host); in sh_mmcif_end_cmd()
1140 host->sd_error = false; in sh_mmcif_end_cmd()
1148 sh_mmcif_get_response(host, cmd); in sh_mmcif_end_cmd()
1157 init_completion(&host->dma_complete); in sh_mmcif_end_cmd()
1160 if (host->chan_rx) in sh_mmcif_end_cmd()
1161 sh_mmcif_start_dma_rx(host); in sh_mmcif_end_cmd()
1163 if (host->chan_tx) in sh_mmcif_end_cmd()
1164 sh_mmcif_start_dma_tx(host); in sh_mmcif_end_cmd()
1167 if (!host->dma_active) { in sh_mmcif_end_cmd()
1168 data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode); in sh_mmcif_end_cmd()
1173 time = wait_for_completion_interruptible_timeout(&host->dma_complete, in sh_mmcif_end_cmd()
1174 host->timeout); in sh_mmcif_end_cmd()
1177 dma_unmap_sg(host->chan_rx->device->dev, in sh_mmcif_end_cmd()
1181 dma_unmap_sg(host->chan_tx->device->dev, in sh_mmcif_end_cmd()
1185 if (host->sd_error) { in sh_mmcif_end_cmd()
1186 dev_err(host->mmc->parent, in sh_mmcif_end_cmd()
1189 data->error = sh_mmcif_error_manage(host); in sh_mmcif_end_cmd()
1191 dev_err(host->mmc->parent, "DMA timeout!\n"); in sh_mmcif_end_cmd()
1194 dev_err(host->mmc->parent, in sh_mmcif_end_cmd()
1198 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, in sh_mmcif_end_cmd()
1200 host->dma_active = false; in sh_mmcif_end_cmd()
1206 dmaengine_terminate_sync(host->chan_rx); in sh_mmcif_end_cmd()
1208 dmaengine_terminate_sync(host->chan_tx); in sh_mmcif_end_cmd()
1216 struct sh_mmcif_host *host = dev_id; in sh_mmcif_irqt() local
1218 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_irqt()
1223 spin_lock_irqsave(&host->lock, flags); in sh_mmcif_irqt()
1224 wait_work = host->wait_for; in sh_mmcif_irqt()
1225 spin_unlock_irqrestore(&host->lock, flags); in sh_mmcif_irqt()
1227 cancel_delayed_work_sync(&host->timeout_work); in sh_mmcif_irqt()
1229 mutex_lock(&host->thread_lock); in sh_mmcif_irqt()
1231 mrq = host->mrq; in sh_mmcif_irqt()
1234 host->state, host->wait_for); in sh_mmcif_irqt()
1235 mutex_unlock(&host->thread_lock); in sh_mmcif_irqt()
1246 mutex_unlock(&host->thread_lock); in sh_mmcif_irqt()
1250 wait = sh_mmcif_end_cmd(host); in sh_mmcif_irqt()
1254 wait = sh_mmcif_mread_block(host); in sh_mmcif_irqt()
1258 wait = sh_mmcif_read_block(host); in sh_mmcif_irqt()
1262 wait = sh_mmcif_mwrite_block(host); in sh_mmcif_irqt()
1266 wait = sh_mmcif_write_block(host); in sh_mmcif_irqt()
1269 if (host->sd_error) { in sh_mmcif_irqt()
1270 mrq->stop->error = sh_mmcif_error_manage(host); in sh_mmcif_irqt()
1274 sh_mmcif_get_cmd12response(host, mrq->stop); in sh_mmcif_irqt()
1279 if (host->sd_error) { in sh_mmcif_irqt()
1280 mrq->data->error = sh_mmcif_error_manage(host); in sh_mmcif_irqt()
1289 schedule_delayed_work(&host->timeout_work, host->timeout); in sh_mmcif_irqt()
1291 mutex_unlock(&host->thread_lock); in sh_mmcif_irqt()
1295 if (host->wait_for != MMCIF_WAIT_FOR_STOP) { in sh_mmcif_irqt()
1302 sh_mmcif_stop_cmd(host, mrq); in sh_mmcif_irqt()
1304 schedule_delayed_work(&host->timeout_work, host->timeout); in sh_mmcif_irqt()
1305 mutex_unlock(&host->thread_lock); in sh_mmcif_irqt()
1311 host->wait_for = MMCIF_WAIT_FOR_REQUEST; in sh_mmcif_irqt()
1312 host->state = STATE_IDLE; in sh_mmcif_irqt()
1313 host->mrq = NULL; in sh_mmcif_irqt()
1314 mmc_request_done(host->mmc, mrq); in sh_mmcif_irqt()
1316 mutex_unlock(&host->thread_lock); in sh_mmcif_irqt()
1323 struct sh_mmcif_host *host = dev_id; in sh_mmcif_intr() local
1324 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_intr()
1327 state = sh_mmcif_readl(host->addr, MMCIF_CE_INT); in sh_mmcif_intr()
1328 mask = sh_mmcif_readl(host->addr, MMCIF_CE_INT_MASK); in sh_mmcif_intr()
1329 if (host->ccs_enable) in sh_mmcif_intr()
1330 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~(state & mask)); in sh_mmcif_intr()
1332 sh_mmcif_writel(host->addr, MMCIF_CE_INT, INT_CCS | ~(state & mask)); in sh_mmcif_intr()
1333 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state & MASK_CLEAN); in sh_mmcif_intr()
1340 host->sd_error = true; in sh_mmcif_intr()
1344 if (!host->mrq) in sh_mmcif_intr()
1346 if (!host->dma_active) in sh_mmcif_intr()
1348 else if (host->sd_error) in sh_mmcif_intr()
1349 sh_mmcif_dma_complete(host); in sh_mmcif_intr()
1360 struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work); in sh_mmcif_timeout_work() local
1361 struct mmc_request *mrq = host->mrq; in sh_mmcif_timeout_work()
1362 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_timeout_work()
1365 if (host->dying) in sh_mmcif_timeout_work()
1369 spin_lock_irqsave(&host->lock, flags); in sh_mmcif_timeout_work()
1370 if (host->state == STATE_IDLE) { in sh_mmcif_timeout_work()
1371 spin_unlock_irqrestore(&host->lock, flags); in sh_mmcif_timeout_work()
1376 host->wait_for, mrq->cmd->opcode); in sh_mmcif_timeout_work()
1378 host->state = STATE_TIMEOUT; in sh_mmcif_timeout_work()
1379 spin_unlock_irqrestore(&host->lock, flags); in sh_mmcif_timeout_work()
1385 switch (host->wait_for) { in sh_mmcif_timeout_work()
1387 mrq->cmd->error = sh_mmcif_error_manage(host); in sh_mmcif_timeout_work()
1390 mrq->stop->error = sh_mmcif_error_manage(host); in sh_mmcif_timeout_work()
1398 mrq->data->error = sh_mmcif_error_manage(host); in sh_mmcif_timeout_work()
1404 host->state = STATE_IDLE; in sh_mmcif_timeout_work()
1405 host->wait_for = MMCIF_WAIT_FOR_REQUEST; in sh_mmcif_timeout_work()
1406 host->mrq = NULL; in sh_mmcif_timeout_work()
1407 mmc_request_done(host->mmc, mrq); in sh_mmcif_timeout_work()
1410 static void sh_mmcif_init_ocr(struct sh_mmcif_host *host) in sh_mmcif_init_ocr() argument
1412 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_init_ocr()
1414 struct mmc_host *mmc = host->mmc; in sh_mmcif_init_ocr()
1431 struct sh_mmcif_host *host; in sh_mmcif_probe() local
1454 host = mmc_priv(mmc); in sh_mmcif_probe()
1455 host->mmc = mmc; in sh_mmcif_probe()
1456 host->addr = reg; in sh_mmcif_probe()
1457 host->timeout = msecs_to_jiffies(10000); in sh_mmcif_probe()
1458 host->ccs_enable = true; in sh_mmcif_probe()
1459 host->clk_ctrl2_enable = false; in sh_mmcif_probe()
1461 host->pd = pdev; in sh_mmcif_probe()
1463 spin_lock_init(&host->lock); in sh_mmcif_probe()
1466 sh_mmcif_init_ocr(host); in sh_mmcif_probe()
1480 platform_set_drvdata(pdev, host); in sh_mmcif_probe()
1482 host->clk = devm_clk_get(dev, NULL); in sh_mmcif_probe()
1483 if (IS_ERR(host->clk)) { in sh_mmcif_probe()
1484 ret = PTR_ERR(host->clk); in sh_mmcif_probe()
1489 ret = clk_prepare_enable(host->clk); in sh_mmcif_probe()
1493 sh_mmcif_clk_setup(host); in sh_mmcif_probe()
1496 host->power = false; in sh_mmcif_probe()
1502 INIT_DELAYED_WORK(&host->timeout_work, sh_mmcif_timeout_work); in sh_mmcif_probe()
1504 sh_mmcif_sync_reset(host); in sh_mmcif_probe()
1505 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); in sh_mmcif_probe()
1509 sh_mmcif_irqt, 0, name, host); in sh_mmcif_probe()
1517 0, "sh_mmc:int", host); in sh_mmcif_probe()
1524 mutex_init(&host->thread_lock); in sh_mmcif_probe()
1533 sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0xffff, in sh_mmcif_probe()
1534 clk_get_rate(host->clk) / 1000000UL); in sh_mmcif_probe()
1537 clk_disable_unprepare(host->clk); in sh_mmcif_probe()
1541 clk_disable_unprepare(host->clk); in sh_mmcif_probe()
1551 struct sh_mmcif_host *host = platform_get_drvdata(pdev); in sh_mmcif_remove() local
1553 host->dying = true; in sh_mmcif_remove()
1554 clk_prepare_enable(host->clk); in sh_mmcif_remove()
1559 mmc_remove_host(host->mmc); in sh_mmcif_remove()
1560 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); in sh_mmcif_remove()
1567 cancel_delayed_work_sync(&host->timeout_work); in sh_mmcif_remove()
1569 clk_disable_unprepare(host->clk); in sh_mmcif_remove()
1570 mmc_free_host(host->mmc); in sh_mmcif_remove()
1578 struct sh_mmcif_host *host = dev_get_drvdata(dev); in sh_mmcif_suspend() local
1581 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); in sh_mmcif_suspend()