mmc/host/sdhci.h

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3  *  linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
7  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
103  * VDD2 - UHS2 or PCIe/NVMe
174 #define SDHCI_INT_ALL_MASK	((unsigned int)-1)
196 #define   SDHCI_CTRL_HS400		0x0005 /* Non-standard */
243 #define  SDHCI_SUPPORT_HS400	0x80000000 /* Non-standard */
252 /* 4C-4F reserved for more max current */
259 /* 55-57 reserved */
264 /* 60-FB reserved */
272 #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */
302 #define SDHCI_DEFAULT_BOUNDARY_ARG   (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12)
304 /* ADMA2 32-bit DMA descriptor size */
307 /* ADMA2 32-bit descriptor */
316 #define SDHCI_ADMA2_MASK	(SDHCI_ADMA2_ALIGN - 1)
320  * alignment for the descriptor table even in 32-bit DMA mode.  Memory
326  * ADMA2 64-bit DMA descriptor size
328  * descriptors for 64-bit addressing mode: 96-bit Descriptor and 128-bit
330  * register, 128-bit Descriptor will be selected.
332 #define SDHCI_ADMA2_64_DESC_SZ(host)	((host)->v4_mode ? 16 : 12)
335  * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte
360  * 48bit command and 136 bit response in 100KHz clock could take upto 2.48ms.
368 	mmc_debugfs_err_stats_inc((host)->mmc, MMC_ERR_##err_name)
380 	unsigned int quirks;	/* Deviations from spec. */
382 /* Controller doesn't honor resets unless we touch the clock register */
394 /* Controller can only DMA from 32-bit aligned addresses */
400 /* Controller needs to be reset after each request to stay stable */
408 /* Controller does not provide transfer-complete interrupt when not busy */
412 /* Controller reports inverted write-protect state */
422 /* Controller cannot do multi-block transfers */
424 /* Controller can only handle 1-bit data transfers */
426 /* Controller needs 10ms delay between applying power and clock */
430 /* Controller reports wrong base clock capability */
436 /* Controller doesn't have HISPD bit field in HI-SPEED SD card */
441 	unsigned int quirks2;	/* More deviations from spec. */
449 /* Controller has a non-standard host control register */
457 /* Controller does not support 64-bit DMA */
461 /* Capability register bit-63 indicates HS400 support */
463 /* forced tuned clock */
467 /* Controller broken with using ACMD23 */
469 /* Broken Clock divider zero in controller */
479  * 32-bit block count may not support eMMC where upper bits of CMD23 are used
480  * for other purposes.  Consequently we support 16-bit block count by default.
481  * Otherwise, SDHCI_QUIRK2_USE_32BIT_BLK_CNT can be selected to use 32-bit
488 	int irq;		/* Device IRQ */
493 	unsigned int bounce_buffer_size;
509 	int flags;		/* Host attributes */
518 #define SDHCI_USE_64_BIT_DMA	(1<<12)	/* Use 64-bit DMA */
524 	unsigned int version;	/* SDHCI spec. version */
526 	unsigned int max_clk;	/* Max possible freq (MHz) */
527 	unsigned int timeout_clk;	/* Timeout freq (KHz) */
529 	unsigned int clk_mul;	/* Clock Muliplier value */
531 	unsigned int clock;	/* Current clock (MHz) */  member
533 	u8 drv_type;		/* Current UHS-I driver type */
534 	bool reinit_uhs;	/* Force UHS-related re-initialization */
550 	unsigned int data_early:1;	/* Data finished before cmd */
553 	unsigned int blocks;	/* remaining PIO blocks */
555 	int sg_count;		/* Mapped sg entries */
556 	int max_adma;		/* Max. length in ADMA descriptor */
567 	unsigned int desc_sz;	/* ADMA current descriptor size */
568 	unsigned int alloc_desc_sz;	/* ADMA descr. max size host supports */
586 	unsigned int            ocr_avail_sdio;	/* OCR bit masks */
587 	unsigned int            ocr_avail_sd;
588 	unsigned int            ocr_avail_mmc;
603 	unsigned int		tuning_done;	/* Condition flag set when CMD19 succeeds */
605 	unsigned int		tuning_count;	/* Timer count for re-tuning */
606 	unsigned int		tuning_mode;	/* Re-tuning mode supported by host */
607 	unsigned int		tuning_err;	/* Error code for re-tuning */
612 	int			tuning_delay;
613 	int			tuning_loop_count;
628 	u32		(*read_l)(struct sdhci_host *host, int reg);
629 	u16		(*read_w)(struct sdhci_host *host, int reg);
630 	u8		(*read_b)(struct sdhci_host *host, int reg);
631 	void		(*write_l)(struct sdhci_host *host, u32 val, int reg);
632 	void		(*write_w)(struct sdhci_host *host, u16 val, int reg);
633 	void		(*write_b)(struct sdhci_host *host, u8 val, int reg);
636 	void	(*set_clock)(struct sdhci_host *host, unsigned int clock);
642 	int		(*set_dma_mask)(struct sdhci_host *host);
643 	int		(*enable_dma)(struct sdhci_host *host);
644 	unsigned int	(*get_max_clock)(struct sdhci_host *host);
645 	unsigned int	(*get_min_clock)(struct sdhci_host *host);
647 	unsigned int	(*get_timeout_clock)(struct sdhci_host *host);
648 	unsigned int	(*get_max_timeout_count)(struct sdhci_host *host);
651 	void		(*set_bus_width)(struct sdhci_host *host, int width);
654 	unsigned int    (*get_ro)(struct sdhci_host *host);
656 	int	(*platform_execute_tuning)(struct sdhci_host *host, u32 opcode);
657 	void	(*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs);
663 				   dma_addr_t addr, int len, unsigned int cmd);
666 					 unsigned int length);
674 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)  in sdhci_writel()
676 	if (unlikely(host->ops->write_l))  in sdhci_writel()
677 		host->ops->write_l(host, val, reg);  in sdhci_writel()
679 		writel(val, host->ioaddr + reg);  in sdhci_writel()
682 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)  in sdhci_writew()
684 	if (unlikely(host->ops->write_w))  in sdhci_writew()
685 		host->ops->write_w(host, val, reg);  in sdhci_writew()
687 		writew(val, host->ioaddr + reg);  in sdhci_writew()
690 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)  in sdhci_writeb()
692 	if (unlikely(host->ops->write_b))  in sdhci_writeb()
693 		host->ops->write_b(host, val, reg);  in sdhci_writeb()
695 		writeb(val, host->ioaddr + reg);  in sdhci_writeb()
698 static inline u32 sdhci_readl(struct sdhci_host *host, int reg)  in sdhci_readl()
700 	if (unlikely(host->ops->read_l))  in sdhci_readl()
701 		return host->ops->read_l(host, reg);  in sdhci_readl()
703 		return readl(host->ioaddr + reg);  in sdhci_readl()
706 static inline u16 sdhci_readw(struct sdhci_host *host, int reg)  in sdhci_readw()
708 	if (unlikely(host->ops->read_w))  in sdhci_readw()
709 		return host->ops->read_w(host, reg);  in sdhci_readw()
711 		return readw(host->ioaddr + reg);  in sdhci_readw()
714 static inline u8 sdhci_readb(struct sdhci_host *host, int reg)  in sdhci_readb()
716 	if (unlikely(host->ops->read_b))  in sdhci_readb()
717 		return host->ops->read_b(host, reg);  in sdhci_readb()
719 		return readb(host->ioaddr + reg);  in sdhci_readb()
724 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)  in sdhci_writel()
726 	writel(val, host->ioaddr + reg);  in sdhci_writel()
729 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)  in sdhci_writew()
731 	writew(val, host->ioaddr + reg);  in sdhci_writew()
734 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)  in sdhci_writeb()
736 	writeb(val, host->ioaddr + reg);  in sdhci_writeb()
739 static inline u32 sdhci_readl(struct sdhci_host *host, int reg)  in sdhci_readl()
741 	return readl(host->ioaddr + reg);  in sdhci_readl()
744 static inline u16 sdhci_readw(struct sdhci_host *host, int reg)  in sdhci_readw()
746 	return readw(host->ioaddr + reg);  in sdhci_readw()
749 static inline u8 sdhci_readb(struct sdhci_host *host, int reg)  in sdhci_readb()
751 	return readb(host->ioaddr + reg);  in sdhci_readb()
761 	return host->private;  in sdhci_priv()
766 int sdhci_setup_host(struct sdhci_host *host);
768 int __sdhci_add_host(struct sdhci_host *host);
769 int sdhci_add_host(struct sdhci_host *host);
770 void sdhci_remove_host(struct sdhci_host *host, int dead);
777 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
778 		   unsigned int *actual_clock);
779 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock);
788 int sdhci_get_cd_nogpio(struct mmc_host *mmc);
789 int sdhci_get_ro(struct mmc_host *mmc);
791 int sdhci_request_atomic(struct mmc_host *mmc, struct mmc_request *mrq);
792 void sdhci_set_bus_width(struct sdhci_host *host, int width);
795 int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
796 int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode);
798 int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
800 void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable);
802 			   dma_addr_t addr, int len, unsigned int cmd);
805 int sdhci_suspend_host(struct sdhci_host *host);
806 int sdhci_resume_host(struct sdhci_host *host);
807 int sdhci_runtime_suspend_host(struct sdhci_host *host);
808 int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset);
813 bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
814 		   int *data_error);