Lines Matching +full:sdhci +full:- +full:8
1 // SPDX-License-Identifier: GPL-2.0-only
27 #include "sdhci.h"
28 #include "sdhci-pltfm.h"
62 #define SDHCI_MAX_WIN_NUM 8
80 dev_err(&pdev->dev, "no mbus dram info\n"); in mv_conf_mbus_windows()
81 return -EINVAL; in mv_conf_mbus_windows()
86 dev_err(&pdev->dev, "cannot get mbus registers\n"); in mv_conf_mbus_windows()
87 return -EINVAL; in mv_conf_mbus_windows()
90 regs = ioremap(res->start, resource_size(res)); in mv_conf_mbus_windows()
92 dev_err(&pdev->dev, "cannot map mbus registers\n"); in mv_conf_mbus_windows()
93 return -ENOMEM; in mv_conf_mbus_windows()
101 for (i = 0; i < dram->num_cs; i++) { in mv_conf_mbus_windows()
102 const struct mbus_dram_window *cs = dram->cs + i; in mv_conf_mbus_windows()
105 writel(((cs->size - 1) & 0xffff0000) | in mv_conf_mbus_windows()
106 (cs->mbus_attr << 8) | in mv_conf_mbus_windows()
107 (dram->mbus_dram_target_id << 4) | 1, in mv_conf_mbus_windows()
110 writel(cs->base, regs + SDHCI_WINDOW_BASE(i)); in mv_conf_mbus_windows()
121 struct device_node *np = pdev->dev.of_node; in armada_38x_quirks()
126 host->quirks &= ~SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN; in armada_38x_quirks()
131 "conf-sdio3"); in armada_38x_quirks()
133 pxa->sdio3_conf_reg = devm_ioremap_resource(&pdev->dev, res); in armada_38x_quirks()
134 if (IS_ERR(pxa->sdio3_conf_reg)) in armada_38x_quirks()
135 return PTR_ERR(pxa->sdio3_conf_reg); in armada_38x_quirks()
138 * According to erratum 'FE-2946959' both SDR50 and DDR50 in armada_38x_quirks()
143 host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50); in armada_38x_quirks()
145 …dev_warn(&pdev->dev, "conf-sdio3 register not found: disabling SDR50 and DDR50 modes.\nConsider up… in armada_38x_quirks()
149 * According to erratum 'ERR-7878951' Armada 38x SDHCI in armada_38x_quirks()
153 if (of_property_read_bool(np, "no-1-8-v")) { in armada_38x_quirks()
154 host->caps &= ~SDHCI_CAN_VDD_180; in armada_38x_quirks()
155 host->mmc->caps &= ~MMC_CAP_1_8V_DDR; in armada_38x_quirks()
157 host->caps &= ~SDHCI_CAN_VDD_330; in armada_38x_quirks()
159 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_USE_SDR50_TUNING); in armada_38x_quirks()
166 struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc)); in pxav3_reset()
167 struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data; in pxav3_reset()
176 if (pdata && 0 != pdata->clk_delay_cycles) { in pxav3_reset()
179 tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); in pxav3_reset()
180 tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK) in pxav3_reset()
183 writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); in pxav3_reset()
196 if (pxa->power_mode == MMC_POWER_UP in pxav3_gen_init_74_clocks()
199 dev_dbg(mmc_dev(host->mmc), in pxav3_gen_init_74_clocks()
200 "%s: slot->power_mode = %d," in pxav3_gen_init_74_clocks()
201 "ios->power_mode = %d\n", in pxav3_gen_init_74_clocks()
203 pxa->power_mode, in pxav3_gen_init_74_clocks()
207 tmp = readw(host->ioaddr + SD_CE_ATA_2); in pxav3_gen_init_74_clocks()
209 writew(tmp, host->ioaddr + SD_CE_ATA_2); in pxav3_gen_init_74_clocks()
212 tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM); in pxav3_gen_init_74_clocks()
214 writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM); in pxav3_gen_init_74_clocks()
221 if ((readw(host->ioaddr + SD_CE_ATA_2) in pxav3_gen_init_74_clocks()
228 dev_warn(mmc_dev(host->mmc), "74 clock interrupt not cleared\n"); in pxav3_gen_init_74_clocks()
231 tmp = readw(host->ioaddr + SD_CE_ATA_2); in pxav3_gen_init_74_clocks()
233 writew(tmp, host->ioaddr + SD_CE_ATA_2); in pxav3_gen_init_74_clocks()
235 pxa->power_mode = power_mode; in pxav3_gen_init_74_clocks()
245 * Set V18_EN -- UHS modes do not work without this. in pxav3_set_uhs_signaling()
273 * FE-2946959 in pxav3_set_uhs_signaling()
275 if (pxa->sdio3_conf_reg) { in pxav3_set_uhs_signaling()
276 u8 reg_val = readb(pxa->sdio3_conf_reg); in pxav3_set_uhs_signaling()
289 writeb(reg_val, pxa->sdio3_conf_reg); in pxav3_set_uhs_signaling()
293 dev_dbg(mmc_dev(host->mmc), in pxav3_set_uhs_signaling()
301 struct mmc_host *mmc = host->mmc; in pxav3_set_power()
302 u8 pwr = host->pwr; in pxav3_set_power()
306 if (host->pwr == pwr) in pxav3_set_power()
309 if (host->pwr == 0) in pxav3_set_power()
312 if (!IS_ERR(mmc->supply.vmmc)) in pxav3_set_power()
313 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); in pxav3_set_power()
337 .compatible = "mrvl,pxav3-mmc",
340 .compatible = "marvell,armada-380-sdhci",
349 struct device_node *np = dev->of_node; in pxav3_get_mmc_pdata()
356 if (!of_property_read_u32(np, "mrvl,clk-delay-cycles", in pxav3_get_mmc_pdata()
358 pdata->clk_delay_cycles = clk_delay_cycles; in pxav3_get_mmc_pdata()
372 struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data; in sdhci_pxav3_probe()
373 struct device *dev = &pdev->dev; in sdhci_pxav3_probe()
374 struct device_node *np = pdev->dev.of_node; in sdhci_pxav3_probe()
387 pxa->clk_io = devm_clk_get(dev, "io"); in sdhci_pxav3_probe()
388 if (IS_ERR(pxa->clk_io)) in sdhci_pxav3_probe()
389 pxa->clk_io = devm_clk_get(dev, NULL); in sdhci_pxav3_probe()
390 if (IS_ERR(pxa->clk_io)) { in sdhci_pxav3_probe()
392 ret = PTR_ERR(pxa->clk_io); in sdhci_pxav3_probe()
395 pltfm_host->clk = pxa->clk_io; in sdhci_pxav3_probe()
396 clk_prepare_enable(pxa->clk_io); in sdhci_pxav3_probe()
398 pxa->clk_core = devm_clk_get(dev, "core"); in sdhci_pxav3_probe()
399 if (!IS_ERR(pxa->clk_core)) in sdhci_pxav3_probe()
400 clk_prepare_enable(pxa->clk_core); in sdhci_pxav3_probe()
402 /* enable 1/8V DDR capable */ in sdhci_pxav3_probe()
403 host->mmc->caps |= MMC_CAP_1_8V_DDR; in sdhci_pxav3_probe()
405 if (of_device_is_compatible(np, "marvell,armada-380-sdhci")) { in sdhci_pxav3_probe()
414 match = of_match_device(of_match_ptr(sdhci_pxav3_of_match), &pdev->dev); in sdhci_pxav3_probe()
416 ret = mmc_of_parse(host->mmc); in sdhci_pxav3_probe()
421 pdev->dev.platform_data = pdata; in sdhci_pxav3_probe()
423 /* on-chip device */ in sdhci_pxav3_probe()
424 if (pdata->flags & PXA_FLAG_CARD_PERMANENT) in sdhci_pxav3_probe()
425 host->mmc->caps |= MMC_CAP_NONREMOVABLE; in sdhci_pxav3_probe()
427 /* If slot design supports 8 bit data, indicate this to MMC. */ in sdhci_pxav3_probe()
428 if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT) in sdhci_pxav3_probe()
429 host->mmc->caps |= MMC_CAP_8_BIT_DATA; in sdhci_pxav3_probe()
431 if (pdata->quirks) in sdhci_pxav3_probe()
432 host->quirks |= pdata->quirks; in sdhci_pxav3_probe()
433 if (pdata->quirks2) in sdhci_pxav3_probe()
434 host->quirks2 |= pdata->quirks2; in sdhci_pxav3_probe()
435 if (pdata->host_caps) in sdhci_pxav3_probe()
436 host->mmc->caps |= pdata->host_caps; in sdhci_pxav3_probe()
437 if (pdata->host_caps2) in sdhci_pxav3_probe()
438 host->mmc->caps2 |= pdata->host_caps2; in sdhci_pxav3_probe()
439 if (pdata->pm_caps) in sdhci_pxav3_probe()
440 host->mmc->pm_caps |= pdata->pm_caps; in sdhci_pxav3_probe()
443 pm_runtime_get_noresume(&pdev->dev); in sdhci_pxav3_probe()
444 pm_runtime_set_active(&pdev->dev); in sdhci_pxav3_probe()
445 pm_runtime_set_autosuspend_delay(&pdev->dev, PXAV3_RPM_DELAY_MS); in sdhci_pxav3_probe()
446 pm_runtime_use_autosuspend(&pdev->dev); in sdhci_pxav3_probe()
447 pm_runtime_enable(&pdev->dev); in sdhci_pxav3_probe()
448 pm_suspend_ignore_children(&pdev->dev, 1); in sdhci_pxav3_probe()
454 if (host->mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ) in sdhci_pxav3_probe()
455 device_init_wakeup(&pdev->dev, 1); in sdhci_pxav3_probe()
457 pm_runtime_put_autosuspend(&pdev->dev); in sdhci_pxav3_probe()
462 pm_runtime_disable(&pdev->dev); in sdhci_pxav3_probe()
463 pm_runtime_put_noidle(&pdev->dev); in sdhci_pxav3_probe()
466 clk_disable_unprepare(pxa->clk_io); in sdhci_pxav3_probe()
467 clk_disable_unprepare(pxa->clk_core); in sdhci_pxav3_probe()
479 pm_runtime_get_sync(&pdev->dev); in sdhci_pxav3_remove()
480 pm_runtime_disable(&pdev->dev); in sdhci_pxav3_remove()
481 pm_runtime_put_noidle(&pdev->dev); in sdhci_pxav3_remove()
485 clk_disable_unprepare(pxa->clk_io); in sdhci_pxav3_remove()
486 clk_disable_unprepare(pxa->clk_core); in sdhci_pxav3_remove()
498 if (host->tuning_mode != SDHCI_TUNING_MODE_3) in sdhci_pxav3_suspend()
499 mmc_retune_needed(host->mmc); in sdhci_pxav3_suspend()
533 if (host->tuning_mode != SDHCI_TUNING_MODE_3) in sdhci_pxav3_runtime_suspend()
534 mmc_retune_needed(host->mmc); in sdhci_pxav3_runtime_suspend()
536 clk_disable_unprepare(pxa->clk_io); in sdhci_pxav3_runtime_suspend()
537 if (!IS_ERR(pxa->clk_core)) in sdhci_pxav3_runtime_suspend()
538 clk_disable_unprepare(pxa->clk_core); in sdhci_pxav3_runtime_suspend()
549 clk_prepare_enable(pxa->clk_io); in sdhci_pxav3_runtime_resume()
550 if (!IS_ERR(pxa->clk_core)) in sdhci_pxav3_runtime_resume()
551 clk_prepare_enable(pxa->clk_core); in sdhci_pxav3_runtime_resume()
565 .name = "sdhci-pxav3",
576 MODULE_DESCRIPTION("SDHCI driver for pxav3");