Lines Matching +full:ssc +full:- +full:controller
1 // SPDX-License-Identifier: GPL-2.0+
7 * Version: v0.9.0 (2019-08-08)
18 #include "sdhci-cqhci.h"
19 #include "sdhci-pci.h"
380 if (!host->tuning_done) { in __sdhci_execute_tuning_9750()
393 if (!host->tuning_done) { in __sdhci_execute_tuning_9750()
395 mmc_hostname(host->mmc)); in __sdhci_execute_tuning_9750()
396 return -ETIMEDOUT; in __sdhci_execute_tuning_9750()
400 mmc_hostname(host->mmc)); in __sdhci_execute_tuning_9750()
403 return -EAGAIN; in __sdhci_execute_tuning_9750()
408 host->mmc->retune_period = 0; in gl9750_execute_tuning()
409 if (host->tuning_mode == SDHCI_TUNING_MODE_1) in gl9750_execute_tuning()
410 host->mmc->retune_period = host->tuning_count; in gl9750_execute_tuning()
413 host->tuning_err = __sdhci_execute_tuning_9750(host, opcode); in gl9750_execute_tuning()
465 u32 ssc; in gl9750_set_ssc() local
469 ssc = sdhci_readl(host, SDHCI_GLI_9750_PLLSSC); in gl9750_set_ssc()
472 ssc &= ~SDHCI_GLI_9750_PLLSSC_PPM; in gl9750_set_ssc()
475 ssc |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_PPM, ppm); in gl9750_set_ssc()
476 sdhci_writel(host, ssc, SDHCI_GLI_9750_PLLSSC); in gl9750_set_ssc()
485 /* set pll to 205MHz and ssc */ in gl9750_set_ssc_pll_205mhz()
494 /* set pll to 100MHz and ssc */ in gl9750_set_ssc_pll_100mhz()
503 /* set pll to 50MHz and ssc */ in gl9750_set_ssc_pll_50mhz()
510 struct mmc_ios *ios = &host->mmc->ios; in sdhci_gl9750_set_clock()
513 host->mmc->actual_clock = 0; in sdhci_gl9750_set_clock()
521 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); in sdhci_gl9750_set_clock()
522 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) { in sdhci_gl9750_set_clock()
523 host->mmc->actual_clock = 205000000; in sdhci_gl9750_set_clock()
541 pdev = slot->chip->pdev; in gl9750_hw_setting()
571 ret = pci_alloc_irq_vectors(slot->chip->pdev, 1, 1, in gli_pcie_enable_msi()
575 mmc_hostname(slot->host->mmc), ret); in gli_pcie_enable_msi()
579 slot->host->irq = pci_irq_vector(slot->chip->pdev, 0); in gli_pcie_enable_msi()
662 u32 ssc; in gl9755_set_ssc() local
666 pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &ssc); in gl9755_set_ssc()
669 ssc &= ~PCI_GLI_9755_PLLSSC_PPM; in gl9755_set_ssc()
672 ssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_PPM, ppm); in gl9755_set_ssc()
673 pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, ssc); in gl9755_set_ssc()
682 /* set pll to 205MHz and ssc */ in gl9755_set_ssc_pll_205mhz()
691 /* set pll to 100MHz and ssc */ in gl9755_set_ssc_pll_100mhz()
700 /* set pll to 50MHz and ssc */ in gl9755_set_ssc_pll_50mhz()
708 struct mmc_ios *ios = &host->mmc->ios; in sdhci_gl9755_set_clock()
712 pdev = slot->chip->pdev; in sdhci_gl9755_set_clock()
713 host->mmc->actual_clock = 0; in sdhci_gl9755_set_clock()
721 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); in sdhci_gl9755_set_clock()
722 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) { in sdhci_gl9755_set_clock()
723 host->mmc->actual_clock = 205000000; in sdhci_gl9755_set_clock()
736 struct pci_dev *pdev = slot->chip->pdev; in gl9755_hw_setting()
747 if (of_property_read_bool(pdev->dev.of_node, "cd-inverted")) in gl9755_hw_setting()
749 if (of_property_read_bool(pdev->dev.of_node, "wp-inverted")) in gl9755_hw_setting()
834 u32 ssc; in gl9767_set_ssc() local
839 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL2, &ssc); in gl9767_set_ssc()
842 ssc &= ~PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM; in gl9767_set_ssc()
845 ssc |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM, ppm); in gl9767_set_ssc()
846 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL2, ssc); in gl9767_set_ssc()
877 /* set pll to 205MHz and ssc */ in gl9767_set_ssc_pll_205mhz()
914 struct mmc_ios *ios = &host->mmc->ios; in sdhci_gl9767_set_clock()
918 pdev = slot->chip->pdev; in sdhci_gl9767_set_clock()
919 host->mmc->actual_clock = 0; in sdhci_gl9767_set_clock()
930 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); in sdhci_gl9767_set_clock()
931 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) { in sdhci_gl9767_set_clock()
932 host->mmc->actual_clock = 205000000; in sdhci_gl9767_set_clock()
951 struct pci_dev *pdev = slot->chip->pdev; in gl9767_hw_setting()
997 pdev = slot->chip->pdev; in gl9767_init_sd_express()
999 if (mmc->ops->get_ro(mmc)) { in gl9767_init_sd_express()
1000 mmc->ios.timing &= ~(MMC_TIMING_SD_EXP | MMC_TIMING_SD_EXP_1_2V); in gl9767_init_sd_express()
1060 mmc->ios.timing &= ~(MMC_TIMING_SD_EXP | MMC_TIMING_SD_EXP_1_2V); in gl9767_init_sd_express()
1081 struct sdhci_host *host = slot->host; in gli_probe_slot_gl9750()
1085 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; in gli_probe_slot_gl9750()
1093 struct sdhci_host *host = slot->host; in gli_probe_slot_gl9755()
1097 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; in gli_probe_slot_gl9755()
1105 struct sdhci_host *host = slot->host; in gli_probe_slot_gl9767()
1110 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; in gli_probe_slot_gl9767()
1111 host->mmc->caps2 |= MMC_CAP2_SD_EXP; in gli_probe_slot_gl9767()
1112 host->mmc_host_ops.init_sd_express = gl9767_init_sd_express; in gli_probe_slot_gl9767()
1122 * SD Host Controller Simplified Spec. 4.20, steps 6~8 are as in sdhci_gli_voltage_switch()
1127 * (8) If 1.8V Signal Enable is cleared by Host Controller, go to in sdhci_gli_voltage_switch()
1133 * ...however, the controller in the NUC10i3FNK4 (a 9755) requires in sdhci_gli_voltage_switch()
1145 * SD Host Controller Simplified Spec. 4.20, steps 6~8 are as in sdhci_gl9767_voltage_switch()
1150 * (8) If 1.8V Signal Enable is cleared by Host Controller, go to in sdhci_gl9767_voltage_switch()
1170 value = readl(host->ioaddr + reg); in sdhci_gl9750_readl()
1184 if (ios->enhanced_strobe) in gl9763e_hs400_enhanced_strobe()
1195 struct pci_dev *pdev = slot->chip->pdev; in gl9763e_set_low_power_negotiation()
1244 struct cqhci_host *cq_host = mmc->cqe_private; in sdhci_gl9763e_cqe_pre_enable()
1268 cqhci_irq(host->mmc, intmask, cmd_error, data_error); in sdhci_gl9763e_cqhci_irq()
1276 struct cqhci_host *cq_host = mmc->cqe_private; in sdhci_gl9763e_cqe_post_disable()
1295 struct device *dev = &slot->chip->pdev->dev; in gl9763e_add_host()
1296 struct sdhci_host *host = slot->host; in gl9763e_add_host()
1307 ret = -ENOMEM; in gl9763e_add_host()
1311 cq_host->mmio = host->ioaddr + SDHCI_GLI_9763E_CQE_BASE_ADDR; in gl9763e_add_host()
1312 cq_host->ops = &sdhci_gl9763e_cqhci_ops; in gl9763e_add_host()
1314 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; in gl9763e_add_host()
1316 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; in gl9763e_add_host()
1318 ret = cqhci_init(cq_host, host->mmc, dma64); in gl9763e_add_host()
1338 struct pci_dev *pdev = slot->chip->pdev; in gli_set_gl9763e()
1374 struct sdhci_pci_slot *slot = chip->slots[0]; in gl9763e_runtime_suspend()
1375 struct sdhci_host *host = slot->host; in gl9763e_runtime_suspend()
1390 struct sdhci_pci_slot *slot = chip->slots[0]; in gl9763e_runtime_resume()
1391 struct sdhci_host *host = slot->host; in gl9763e_runtime_resume()
1394 if (host->mmc->ios.power_mode != MMC_POWER_ON) in gl9763e_runtime_resume()
1407 mmc_hostname(host->mmc)); in gl9763e_runtime_resume()
1424 struct sdhci_pci_slot *slot = chip->slots[0]; in sdhci_pci_gli_resume()
1426 pci_free_irq_vectors(slot->chip->pdev); in sdhci_pci_gli_resume()
1434 struct sdhci_pci_slot *slot = chip->slots[0]; in gl9763e_resume()
1441 ret = cqhci_resume(slot->host->mmc); in gl9763e_resume()
1456 struct sdhci_pci_slot *slot = chip->slots[0]; in gl9763e_suspend()
1460 * Certain SoCs can suspend only with the bus in low- in gl9763e_suspend()
1462 * Re-enable LPM negotiation to allow entering L1 state in gl9763e_suspend()
1467 ret = cqhci_suspend(slot->host->mmc); in gl9763e_suspend()
1471 ret = sdhci_suspend_host(slot->host); in gl9763e_suspend()
1478 cqhci_resume(slot->host->mmc); in gl9763e_suspend()
1487 struct pci_dev *pdev = slot->chip->pdev; in gli_probe_slot_gl9763e()
1488 struct sdhci_host *host = slot->host; in gli_probe_slot_gl9763e()
1491 host->mmc->caps |= MMC_CAP_8_BIT_DATA | in gli_probe_slot_gl9763e()
1494 host->mmc->caps2 |= MMC_CAP2_HS200_1_8V_SDR | in gli_probe_slot_gl9763e()
1503 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; in gli_probe_slot_gl9763e()
1506 host->mmc_host_ops.hs400_enhanced_strobe = in gli_probe_slot_gl9763e()
1518 u32 val = readl(host->ioaddr + (reg & ~3)); in sdhci_gli_readw()
1527 u32 val = readl(host->ioaddr + (reg & ~3)); in sdhci_gli_readb()