465 	u32 ssc;  in gl9750_set_ssc()  local
469 	ssc = sdhci_readl(host, SDHCI_GLI_9750_PLLSSC);  in gl9750_set_ssc()
472 	ssc &= ~SDHCI_GLI_9750_PLLSSC_PPM;  in gl9750_set_ssc()
475 	ssc |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_PPM, ppm);  in gl9750_set_ssc()
476 	sdhci_writel(host, ssc, SDHCI_GLI_9750_PLLSSC);  in gl9750_set_ssc()
485 	/* set pll to 205MHz and ssc */  in gl9750_set_ssc_pll_205mhz()
494 	/* set pll to 100MHz and ssc */  in gl9750_set_ssc_pll_100mhz()
503 	/* set pll to 50MHz and ssc */  in gl9750_set_ssc_pll_50mhz()
662 	u32 ssc;  in gl9755_set_ssc()  local
666 	pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &ssc);  in gl9755_set_ssc()
669 	ssc &= ~PCI_GLI_9755_PLLSSC_PPM;  in gl9755_set_ssc()
672 	ssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_PPM, ppm);  in gl9755_set_ssc()
673 	pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, ssc);  in gl9755_set_ssc()
682 	/* set pll to 205MHz and ssc */  in gl9755_set_ssc_pll_205mhz()
691 	/* set pll to 100MHz and ssc */  in gl9755_set_ssc_pll_100mhz()
700 	/* set pll to 50MHz and ssc */  in gl9755_set_ssc_pll_50mhz()
834 	u32 ssc;  in gl9767_set_ssc()  local
839 	pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL2, &ssc);  in gl9767_set_ssc()
842 	ssc &= ~PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM;  in gl9767_set_ssc()
845 	ssc |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM, ppm);  in gl9767_set_ssc()
846 	pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL2, ssc);  in gl9767_set_ssc()
877 	/* set pll to 205MHz and ssc */  in gl9767_set_ssc_pll_205mhz()