1 // SPDX-License-Identifier: GPL-2.0-or-later
3  * drivers/mmc/host/sdhci-of-sparx5.c
5  * MCHP Sparx5 SoC Secure Digital Host Controller Interface.
17 #include <linux/dma-mapping.h>
20 #include "sdhci-pltfm.h"
46 	((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1)))
64 		 mmc_hostname(host->mmc), len, &addr);  in sdhci_sparx5_adma_write_desc()
66 	offset = addr & (SZ_128M - 1);  in sdhci_sparx5_adma_write_desc()
67 	tmplen = SZ_128M - offset;  in sdhci_sparx5_adma_write_desc()
71 	len -= tmplen;  in sdhci_sparx5_adma_write_desc()
80 	pr_debug("%s: Set Cacheable = 0x%x\n", mmc_hostname(host->mmc), value);  in sparx5_set_cacheable()
83 	regmap_update_bits(sdhci_sparx5->cpu_ctrl,  in sparx5_set_cacheable()
92 	pr_debug("%s: Set DLY_CC = %u\n", mmc_hostname(host->mmc), value);  in sparx5_set_delay()
95 	regmap_update_bits(sdhci_sparx5->cpu_ctrl,  in sparx5_set_delay()
103 	if (!mmc_card_is_removable(host->mmc)) {  in sdhci_sparx5_set_emmc()
110 				 mmc_hostname(host->mmc), value);  in sdhci_sparx5_set_emmc()
120 	pr_debug("%s: Toggle EMMC_CTRL.EMMC_RST_N\n", mmc_hostname(host->mmc));  in sdhci_sparx5_reset_emmc()
134 	pr_debug("%s: *** RESET: mask %d\n", mmc_hostname(host->mmc), mask);  in sdhci_sparx5_reset()
161 	const char *syscon = "microchip,sparx5-cpu-syscon";  in sdhci_sparx5_probe()
165 	struct device_node *np = pdev->dev.of_node;  in sdhci_sparx5_probe()
178 	extra = DIV_ROUND_UP_ULL(dma_get_required_mask(&pdev->dev), SZ_128M);  in sdhci_sparx5_probe()
181 	host->adma_table_cnt += extra;  in sdhci_sparx5_probe()
185 	sdhci_sparx5->host = host;  in sdhci_sparx5_probe()
187 	pltfm_host->clk = devm_clk_get_enabled(&pdev->dev, "core");  in sdhci_sparx5_probe()
188 	if (IS_ERR(pltfm_host->clk)) {  in sdhci_sparx5_probe()
189 		ret = PTR_ERR(pltfm_host->clk);  in sdhci_sparx5_probe()
190 		dev_err(&pdev->dev, "failed to get and enable core clk: %d\n", ret);  in sdhci_sparx5_probe()
194 	if (!of_property_read_u32(np, "microchip,clock-delay", &value) &&  in sdhci_sparx5_probe()
196 		sdhci_sparx5->delay_clock = value;  in sdhci_sparx5_probe()
200 	ret = mmc_of_parse(host->mmc);  in sdhci_sparx5_probe()
204 	sdhci_sparx5->cpu_ctrl = syscon_regmap_lookup_by_compatible(syscon);  in sdhci_sparx5_probe()
205 	if (IS_ERR(sdhci_sparx5->cpu_ctrl)) {  in sdhci_sparx5_probe()
206 		dev_err(&pdev->dev, "No CPU syscon regmap !\n");  in sdhci_sparx5_probe()
207 		ret = PTR_ERR(sdhci_sparx5->cpu_ctrl);  in sdhci_sparx5_probe()
211 	if (sdhci_sparx5->delay_clock >= 0)  in sdhci_sparx5_probe()
212 		sparx5_set_delay(host, sdhci_sparx5->delay_clock);  in sdhci_sparx5_probe()
214 	if (!mmc_card_is_removable(host->mmc)) {  in sdhci_sparx5_probe()
220 		host->mmc->caps2 |= (MMC_CAP2_NO_SDIO|MMC_CAP2_NO_SD);  in sdhci_sparx5_probe()
227 	/* Set AXI bus master to use un-cached access (for DMA) */  in sdhci_sparx5_probe()
228 	if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA) &&  in sdhci_sparx5_probe()
233 		 mmc_hostname(host->mmc), sdhci_readl(host, MSHC2_VERSION));  in sdhci_sparx5_probe()
235 		 mmc_hostname(host->mmc), sdhci_readl(host, MSHC2_TYPE));  in sdhci_sparx5_probe()
245 	{ .compatible = "microchip,dw-sparx5-sdhci" },
252 		.name = "sdhci-sparx5",
263 MODULE_DESCRIPTION("Sparx5 SDHCI OF driver");