3  * Freescale eSDHC controller driver.
27 #include "sdhci-esdhc.h"
71 	{ .compatible = "fsl,ls1021a-esdhc", .data = &ls1021a_esdhc_clk},
72 	{ .compatible = "fsl,ls1043a-esdhc", .data = &ls1043a_esdhc_clk},
73 	{ .compatible = "fsl,ls1046a-esdhc", .data = &ls1046a_esdhc_clk},
74 	{ .compatible = "fsl,ls1012a-esdhc", .data = &ls1012a_esdhc_clk},
75 	{ .compatible = "fsl,p1010-esdhc",   .data = &p1010_esdhc_clk},
76 	{ .compatible = "fsl,mpc8379-esdhc" },
77 	{ .compatible = "fsl,mpc8536-esdhc" },
78 	{ .compatible = "fsl,esdhc" },
101  * esdhc_readl_fixup - Fixup the value read from incompatible eSDHC register
106  * @value: 32bit eSDHC register value on spec_reg address
108  * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC
110  * address, register function, bit position and function between eSDHC spec
119 	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);  in esdhc_readl_fixup()  local
123 	 * The bit of ADMA flag in eSDHC is not compatible with standard  in esdhc_readl_fixup()
125 	 * supported by eSDHC.  in esdhc_readl_fixup()
126 	 * And for many FSL eSDHC controller, the reset value of field  in esdhc_readl_fixup()
131 		if (esdhc->vendor_ver > VENDOR_V_22) {  in esdhc_readl_fixup()
156 		if (esdhc->quirk_ignore_data_inhibit)  in esdhc_readl_fixup()
180 	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);  in esdhc_readw_fixup()  local
191 	/* Workaround for T4240-R1.0-R2.0 eSDHC which has incorrect  in esdhc_readw_fixup()
195 	    (esdhc->quirk_incorrect_hostver))  in esdhc_readw_fixup()
225  *			written into eSDHC register.
230  * @old_value: 32bit eSDHC register value on spec_reg address
232  * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC
234  * address, register function, bit position and function between eSDHC spec
300 	 * eSDHC doesn't have a standard power control register, so we do  in esdhc_writeb_fixup()
426 	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);  in esdhc_be_writew()  local
441 		    esdhc->in_sw_tuning) {  in esdhc_be_writew()
452 	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);  in esdhc_le_writew()  local
467 		    esdhc->in_sw_tuning) {  in esdhc_le_writew()
507 	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);  in esdhc_of_adma_workaround()  local
514 		     (esdhc->vendor_ver == VENDOR_V_23);  in esdhc_of_adma_workaround()
536 	if (of_device_is_compatible(dev->of_node, "fsl,ls1043a-esdhc") ||  in esdhc_of_enable_dma()
537 	    of_device_is_compatible(dev->of_node, "fsl,ls1046a-esdhc")) {  in esdhc_of_enable_dma()
557 	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);  in esdhc_of_get_max_clock()  local
559 	if (esdhc->peripheral_clock)  in esdhc_of_get_max_clock()
560 		return esdhc->peripheral_clock;  in esdhc_of_get_max_clock()
568 	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);  in esdhc_of_get_min_clock()  local
571 	if (esdhc->peripheral_clock)  in esdhc_of_get_min_clock()
572 		clock = esdhc->peripheral_clock;  in esdhc_of_get_min_clock()
581 	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);  in esdhc_clock_enable()  local
588 	 * IPGEN/HCKEN/PEREN bits exist on eSDHC whose vendor version  in esdhc_clock_enable()
591 	if (esdhc->vendor_ver <= VENDOR_V_22)  in esdhc_clock_enable()
609 	while (esdhc->vendor_ver > VENDOR_V_22) {  in esdhc_clock_enable()
652 	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);  in esdhc_of_set_clock()  local
665 	if (esdhc->vendor_ver < VENDOR_V_23)  in esdhc_of_set_clock()
670 	    esdhc->clk_fixup && host->mmc->ios.timing == MMC_TIMING_LEGACY)  in esdhc_of_set_clock()
671 		clock_fixup = esdhc->clk_fixup->sd_dflt_max_clk;  in esdhc_of_set_clock()
672 	else if (esdhc->clk_fixup)  in esdhc_of_set_clock()
673 		clock_fixup = esdhc->clk_fixup->max_clk[host->mmc->ios.timing];  in esdhc_of_set_clock()
685 	esdhc->div_ratio = pre_div * div;  in esdhc_of_set_clock()
688 	if (esdhc->quirk_limited_clk_division &&  in esdhc_of_set_clock()
692 		if (esdhc->div_ratio <= 4) {  in esdhc_of_set_clock()
695 		} else if (esdhc->div_ratio <= 8) {  in esdhc_of_set_clock()
698 		} else if (esdhc->div_ratio <= 12) {  in esdhc_of_set_clock()
705 		esdhc->div_ratio = pre_div * div;  in esdhc_of_set_clock()
708 	host->mmc->actual_clock = host->max_clk / esdhc->div_ratio;  in esdhc_of_set_clock()
730 	while (esdhc->vendor_ver > VENDOR_V_22) {  in esdhc_of_set_clock()
806 	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);  in esdhc_reset()  local
813 	if (esdhc->quirk_delay_before_data_reset &&  in esdhc_reset()
819 	 * Save bus-width for eSDHC whose vendor version is 2.2  in esdhc_reset()
823 	    (esdhc->vendor_ver <= VENDOR_V_22)) {  in esdhc_reset()
831 	 * Restore bus-width setting and interrupt registers for eSDHC  in esdhc_reset()
835 	    (esdhc->vendor_ver <= VENDOR_V_22)) {  in esdhc_reset()
846 	 * Some bits have to be cleaned manually for eSDHC whose spec  in esdhc_reset()
850 	    (esdhc->spec_ver >= SDHCI_SPEC_300)) {  in esdhc_reset()
859 		if (esdhc->quirk_unreliable_pulse_detection) {  in esdhc_reset()
1004 	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);  in esdhc_prepare_sw_tuning()  local
1007 	if (esdhc->quirk_tuning_erratum_type1) {  in esdhc_prepare_sw_tuning()
1008 		*window_start = 5 * esdhc->div_ratio;  in esdhc_prepare_sw_tuning()
1009 		*window_end = 3 * esdhc->div_ratio;  in esdhc_prepare_sw_tuning()
1026 	if (abs(start_ptr - end_ptr) > (4 * esdhc->div_ratio + 2)) {  in esdhc_prepare_sw_tuning()
1027 		*window_start = 8 * esdhc->div_ratio;  in esdhc_prepare_sw_tuning()
1028 		*window_end = 4 * esdhc->div_ratio;  in esdhc_prepare_sw_tuning()
1030 		*window_start = 5 * esdhc->div_ratio;  in esdhc_prepare_sw_tuning()
1031 		*window_end = 3 * esdhc->div_ratio;  in esdhc_prepare_sw_tuning()
1040 	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);  in esdhc_execute_sw_tuning()  local
1056 	esdhc->in_sw_tuning = true;  in esdhc_execute_sw_tuning()
1058 	esdhc->in_sw_tuning = false;  in esdhc_execute_sw_tuning()
1066 	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);  in esdhc_execute_tuning()  local
1076 	clk = esdhc->peripheral_clock / 3;  in esdhc_execute_tuning()
1083 	 * The eSDHC controller takes the data timeout value into account  in esdhc_execute_tuning()
1096 		if (esdhc->quirk_limited_clk_division &&  in esdhc_execute_tuning()
1111 		 * tuning may succeed although eSDHC might not have  in esdhc_execute_tuning()
1114 		if (esdhc->quirk_tuning_erratum_type2 &&  in esdhc_execute_tuning()
1119 			    (4 * esdhc->div_ratio + 2))  in esdhc_execute_tuning()
1128 		    (esdhc->quirk_tuning_erratum_type1 ||  in esdhc_execute_tuning()
1129 		     esdhc->quirk_tuning_erratum_type2)) {  in esdhc_execute_tuning()
1151 				clk = host->max_clk / (esdhc->div_ratio + 1);  in esdhc_execute_tuning()
1220 	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);  in esdhc_irq()  local
1223 	if (esdhc->quirk_trans_complete_erratum) {  in esdhc_irq()
1346 	struct sdhci_esdhc *esdhc;  in esdhc_init()  local
1353 	esdhc = sdhci_pltfm_priv(pltfm_host);  in esdhc_init()
1356 	esdhc->vendor_ver = (host_ver & SDHCI_VENDOR_VER_MASK) >>  in esdhc_init()
1358 	esdhc->spec_ver = host_ver & SDHCI_SPEC_VER_MASK;  in esdhc_init()
1360 		esdhc->quirk_incorrect_hostver = true;  in esdhc_init()
1362 		esdhc->quirk_incorrect_hostver = false;  in esdhc_init()
1365 		esdhc->quirk_limited_clk_division = true;  in esdhc_init()
1367 		esdhc->quirk_limited_clk_division = false;  in esdhc_init()
1370 		esdhc->quirk_unreliable_pulse_detection = true;  in esdhc_init()
1372 		esdhc->quirk_unreliable_pulse_detection = false;  in esdhc_init()
1376 		esdhc->clk_fixup = match->data;  in esdhc_init()
1379 	if (of_device_is_compatible(np, "fsl,p2020-esdhc")) {  in esdhc_init()
1380 		esdhc->quirk_delay_before_data_reset = true;  in esdhc_init()
1381 		esdhc->quirk_trans_complete_erratum = true;  in esdhc_init()
1387 		 * esdhc->peripheral_clock would be assigned with a value  in esdhc_init()
1388 		 * which is eSDHC base clock when use periperal clock.  in esdhc_init()
1390 		 * API is peripheral clock while the eSDHC base clock is  in esdhc_init()
1393 		if (of_device_is_compatible(np, "fsl,ls1046a-esdhc") ||  in esdhc_init()
1394 		    of_device_is_compatible(np, "fsl,ls1028a-esdhc") ||  in esdhc_init()
1395 		    of_device_is_compatible(np, "fsl,ls1088a-esdhc"))  in esdhc_init()
1396 			esdhc->peripheral_clock = clk_get_rate(clk) / 2;  in esdhc_init()
1398 			esdhc->peripheral_clock = clk_get_rate(clk);  in esdhc_init()
1410 	if (esdhc->peripheral_clock)  in esdhc_init()
1429 	struct sdhci_esdhc *esdhc;  in sdhci_esdhc_probe()  local
1455 	esdhc = sdhci_pltfm_priv(pltfm_host);  in sdhci_esdhc_probe()
1457 		esdhc->quirk_tuning_erratum_type1 = true;  in sdhci_esdhc_probe()
1459 		esdhc->quirk_tuning_erratum_type1 = false;  in sdhci_esdhc_probe()
1462 		esdhc->quirk_tuning_erratum_type2 = true;  in sdhci_esdhc_probe()
1464 		esdhc->quirk_tuning_erratum_type2 = false;  in sdhci_esdhc_probe()
1466 	if (esdhc->vendor_ver == VENDOR_V_22)  in sdhci_esdhc_probe()
1469 	if (esdhc->vendor_ver > VENDOR_V_22)  in sdhci_esdhc_probe()
1472 	tp = of_find_compatible_node(NULL, NULL, "fsl,p2020-esdhc");  in sdhci_esdhc_probe()
1479 	if (of_device_is_compatible(np, "fsl,p5040-esdhc") ||  in sdhci_esdhc_probe()
1480 	    of_device_is_compatible(np, "fsl,p5020-esdhc") ||  in sdhci_esdhc_probe()
1481 	    of_device_is_compatible(np, "fsl,p4080-esdhc") ||  in sdhci_esdhc_probe()
1482 	    of_device_is_compatible(np, "fsl,p1020-esdhc") ||  in sdhci_esdhc_probe()
1483 	    of_device_is_compatible(np, "fsl,t1040-esdhc"))  in sdhci_esdhc_probe()
1486 	if (of_device_is_compatible(np, "fsl,ls1021a-esdhc"))  in sdhci_esdhc_probe()
1489 	esdhc->quirk_ignore_data_inhibit = false;  in sdhci_esdhc_probe()
1490 	if (of_device_is_compatible(np, "fsl,p2020-esdhc")) {  in sdhci_esdhc_probe()
1496 		esdhc->quirk_ignore_data_inhibit = true;  in sdhci_esdhc_probe()
1518 		.name = "sdhci-esdhc",
1529 MODULE_DESCRIPTION("SDHCI OF driver for Freescale MPC eSDHC");