203  * met at 25MHz for Default Speed mode, those controllers work at
204  * 19MHz instead
401 		 * requirements met at 25MHz for Default Speed mode,  in sdhci_arasan_set_clock()
402 		 * those controllers work at 19MHz instead.  in sdhci_arasan_set_clock()
751 		/* For 50MHz clock, 30 Taps are available */  in sdhci_zynqmp_sdcardclk_set_phase()
752 		tap_max = 30;  in sdhci_zynqmp_sdcardclk_set_phase()
755 		/* For 100MHz clock, 15 Taps are available */  in sdhci_zynqmp_sdcardclk_set_phase()
760 		/* For 200MHz clock, 8 Taps are available */  in sdhci_zynqmp_sdcardclk_set_phase()
820 		/* For 50MHz clock, 120 Taps are available */  in sdhci_zynqmp_sampleclk_set_phase()
824 		/* For 100MHz clock, 60 Taps are available */  in sdhci_zynqmp_sampleclk_set_phase()
829 		/* For 200MHz clock, 30 Taps are available */  in sdhci_zynqmp_sampleclk_set_phase()
830 		tap_max = 30;  in sdhci_zynqmp_sampleclk_set_phase()
880 		/* For 50MHz clock, 30 Taps are available */  in sdhci_versal_sdcardclk_set_phase()
881 		tap_max = 30;  in sdhci_versal_sdcardclk_set_phase()
884 		/* For 100MHz clock, 15 Taps are available */  in sdhci_versal_sdcardclk_set_phase()
889 		/* For 200MHz clock, 8 Taps are available */  in sdhci_versal_sdcardclk_set_phase()
947 		/* For 50MHz clock, 120 Taps are available */  in sdhci_versal_sampleclk_set_phase()
951 		/* For 100MHz clock, 60 Taps are available */  in sdhci_versal_sampleclk_set_phase()
956 		/* For 200MHz clock, 30 Taps are available */  in sdhci_versal_sampleclk_set_phase()
957 		tap_max = 30;  in sdhci_versal_sampleclk_set_phase()
1005 		 /* For 200MHz clock, 32 Taps are available */  in sdhci_versal_net_emmc_sdcardclk_set_phase()
1171  * The corecfg_baseclkfreq is supposed to contain the MHz of clk_xin.  This
1189 	u32 mhz = DIV_ROUND_CLOSEST_ULL(clk_get_rate(pltfm_host->clk), 1000000);  in sdhci_arasan_update_baseclkfreq()  local
1202 	sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz);  in sdhci_arasan_update_baseclkfreq()
1739 	u32 mhz, node_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 : NODE_SD_1;  in sdhci_zynqmp_set_dynamic_config()  local
1763 	mhz = DIV_ROUND_CLOSEST_ULL(clk_get_rate(pltfm_host->clk), 1000000);  in sdhci_zynqmp_set_dynamic_config()
1764 	if (mhz > 100 && mhz <= 200)  in sdhci_zynqmp_set_dynamic_config()
1765 		mhz = 200;  in sdhci_zynqmp_set_dynamic_config()
1766 	else if (mhz > 50 && mhz <= 100)  in sdhci_zynqmp_set_dynamic_config()
1767 		mhz = 100;  in sdhci_zynqmp_set_dynamic_config()
1768 	else if (mhz > 25 && mhz <= 50)  in sdhci_zynqmp_set_dynamic_config()
1769 		mhz = 50;  in sdhci_zynqmp_set_dynamic_config()
1771 		mhz = 25;  in sdhci_zynqmp_set_dynamic_config()
1773 	ret = zynqmp_pm_set_sd_config(node_id, SD_CONFIG_BASECLK, mhz);  in sdhci_zynqmp_set_dynamic_config()