70 /* Tuning bits */
106 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
154 /* The IP supports manual tuning process */
156 /* The IP supports standard tuning process */
234 	unsigned int tuning_step;       /* The delay cell steps in tuning procedure */
235 	unsigned int tuning_start_tap;	/* The start delay cell point in tuning procedure */
445 /* Enable the auto tuning circuit to check the CMD line and BUS line */
468 	 * For USDHC, auto tuning circuit can not handle the async sdio  in usdhc_auto_tuning_mode_sel_and_en()
471 	 * tuning circuit check these 4 data lines, include the DAT[1],  in usdhc_auto_tuning_mode_sel_and_en()
475 	 * device, config the auto tuning circuit only check DAT[0] and CMD  in usdhc_auto_tuning_mode_sel_and_en()
654 				/* the std tuning bits is in ACMD12_ERR for imx6sl */  in esdhc_readw_le()
768 				 * tuning, when send tuning command, usdhc will  in esdhc_writew_le()
891 				 * the tuning bits should be kept during reset  in esdhc_writeb_le()
1056 	/* Reset the tuning circuit */  in esdhc_reset_tuning()
1076 				 "Warning! clear execute tuning bit failed\n");  in esdhc_reset_tuning()
1105 	 * DDR50, normally does not require tuning for DDR50 mode.  in usdhc_execute_tuning()
1111 	 * Reset tuning circuit logic. If not, the previous tuning result  in usdhc_execute_tuning()
1112 	 * will impact current tuning, make current tuning can't set the  in usdhc_execute_tuning()
1117 	/* If tuning done, enable auto tuning */  in usdhc_execute_tuning()
1130 	/* FIXME: delay a bit for card to be ready for next tuning due to errors */  in esdhc_prepare_tuning()
1133 	/* IC suggest to reset USDHC before every tuning command */  in esdhc_prepare_tuning()
1139 		"warning! RESET_ALL never complete before sending tuning command\n");  in esdhc_prepare_tuning()
1147 		"tuning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",  in esdhc_prepare_tuning()
1173 		/* find the mininum delay first which can pass tuning */  in esdhc_executing_tuning()
1181 		/* find the maxinum delay which can not pass tuning */  in esdhc_executing_tuning()
1210 	dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n",  in esdhc_executing_tuning()
1513 			/* Disable the CMD CRC check for tuning, if not, need to  in sdhci_esdhc_imx_hwinit()
1514 			 * add some delay after every tuning command, because  in sdhci_esdhc_imx_hwinit()
1515 			 * hardware standard tuning logic will directly go to next  in sdhci_esdhc_imx_hwinit()
1517 			 * the card side to finally send out the tuning data, trigger  in sdhci_esdhc_imx_hwinit()
1519 			 * the next tuning command some eMMC card will stuck, can't  in sdhci_esdhc_imx_hwinit()
1520 			 * response, block the tuning procedure or the first command  in sdhci_esdhc_imx_hwinit()
1521 			 * after the whole tuning procedure always can't get any response.  in sdhci_esdhc_imx_hwinit()
1529 			 * the manual tuning can work.  in sdhci_esdhc_imx_hwinit()
1563 	 * the case after tuning, so ensure the buffer is drained.  in esdhc_cqe_enable()
1635 	of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step);  in sdhci_esdhc_imx_probe_dt()
1636 	of_property_read_u32(np, "fsl,tuning-start-tap",  in sdhci_esdhc_imx_probe_dt()
1744 		/* clear tuning bits in case ROM has set it already */  in sdhci_esdhc_imx_probe()