Lines Matching full:esdhc

3  * Freescale eSDHC i.MX controller driver for the platform bus.
30 #include "sdhci-esdhc.h"
127  * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC:
128  * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
129  * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
130  * Define this macro DMA error INT for fsl eSDHC
150  * The flag tells that the ESDHC controller is an USDHC block that is
221  * struct esdhc_platform_data - platform data for esdhc on i.MX
364 	{ .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
365 	{ .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
366 	{ .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
367 	{ .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
406 #define DRIVER_NAME "sdhci-esdhc-imx"
422 	ESDHC_IMX_DUMP("========= ESDHC IMX DEBUG STATUS DUMP =========\n");  in esdhc_dump_debug_regs()
511 		/* In FSL esdhc IC module, only bit20 is used to indicate the  in esdhc_readl_le()
512 		 * ADMA2 capability of esdhc, but this bit is messed up on  in esdhc_readl_le()
587 			 * card interrupt. This is an eSDHC controller problem  in esdhc_writel_le()
589 			 * and set D3CD bit will make eSDHC re-sample the card  in esdhc_writel_le()
876 			 * The esdhc has a design violation to SDHC spec which  in esdhc_writeb_le()
878 			 * detection circuit. But esdhc clears its SYSCTL  in esdhc_writeb_le()
900 			 * The eSDHC DAT line software reset clears at least the  in esdhc_writeb_le()
2012 		.name	= "sdhci-esdhc-imx",
2023 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");