33 #define ESDHC_SYS_CTRL_DTOCV_MASK	0x0f
34 #define	ESDHC_CTRL_D3CD			0x08
37 #define ESDHC_VENDOR_SPEC		0xc0
41 #define ESDHC_DEBUG_SEL_AND_STATUS_REG		0xc2
42 #define ESDHC_DEBUG_SEL_REG			0xc3
43 #define ESDHC_DEBUG_SEL_MASK			0xf
51 #define ESDHC_WTMK_LVL			0x44
52 #define  ESDHC_WTMK_DEFAULT_VAL		0x10401040
53 #define  ESDHC_WTMK_LVL_RD_WML_MASK	0x000000FF
54 #define  ESDHC_WTMK_LVL_RD_WML_SHIFT	0
55 #define  ESDHC_WTMK_LVL_WR_WML_MASK	0x00FF0000
59 #define ESDHC_MIX_CTRL			0x48
69 #define  ESDHC_MIX_CTRL_SDHCI_MASK	0xb7
71 #define  ESDHC_MIX_CTRL_TUNING_MASK	0x03c00000
74 #define ESDHC_DLL_CTRL			0x60
79 #define ESDHC_TUNE_CTRL_STATUS		0x68
81 #define  ESDHC_TUNE_CTRL_MIN		0
85 #define ESDHC_STROBE_DLL_CTRL		0x70
86 #define ESDHC_STROBE_DLL_CTRL_ENABLE	(1 << 0)
88 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT	0x7
92 #define ESDHC_STROBE_DLL_STATUS		0x74
94 #define ESDHC_STROBE_DLL_STS_SLV_LOCK	0x1
96 #define ESDHC_VEND_SPEC2		0xc8
99 #define ESDHC_VEND_SPEC2_AUTO_TUNE_4BIT_EN	(0 << 4)
104 #define ESDHC_TUNING_CTRL		0xcc
107 #define ESDHC_TUNING_START_TAP_DEFAULT	0x1
108 #define ESDHC_TUNING_START_TAP_MASK	0x7f
110 #define ESDHC_TUNING_STEP_DEFAULT	0x1
111 #define ESDHC_TUNING_STEP_MASK		0x00070000
121 #define ESDHC_CTRL_4BITBUS		(0x1 << 1)
122 #define ESDHC_CTRL_8BITBUS		(0x2 << 1)
123 #define ESDHC_CTRL_BUSWIDTH_MASK	(0x3 << 1)
135 #define ESDHC_CQHCI_ADDR_OFFSET		0x100
138  * The CMDTYPE of the CMD register (offset 0xE) should be set to
190  * In ADMA mode, it only use the 16 bit block count of the register 0x4
252 	.flags = 0,
400 	void __iomem *base = host->ioaddr + (reg & ~0x3);  in esdhc_clrset_le()
401 	u32 shift = (reg & 0x3) * 8;  in esdhc_clrset_le()
423 	for (i = 0; i < 7; i++) {  in esdhc_dump_debug_regs()
426 		ESDHC_IMX_DUMP("%s:  0x%04x\n", debug_status[i],  in esdhc_dump_debug_regs()
430 	esdhc_clrset_le(host, ESDHC_DEBUG_SEL_MASK, 0, ESDHC_DEBUG_SEL_REG);  in esdhc_dump_debug_regs()
475 	 * device, config the auto tuning circuit only check DAT[0] and CMD  in usdhc_auto_tuning_mode_sel_and_en()
499 		val = fsl_prss & 0x000FFFFF;  in esdhc_readl_le()
500 		/* move dat[0-3] bits */  in esdhc_readl_le()
501 		val |= (fsl_prss & 0x0F000000) >> 4;  in esdhc_readl_le()
503 		val |= (fsl_prss & 0x00800000) << 1;  in esdhc_readl_le()
507 		/* ignore bit[0-15] as it stores cap_1 register val for mx6sl */  in esdhc_readl_le()
509 			val &= 0xffff0000;  in esdhc_readl_le()
527 				val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF;  in esdhc_readl_le()
548 		val = 0;  in esdhc_readl_le()
549 		val |= FIELD_PREP(SDHCI_MAX_CURRENT_330_MASK, 0xFF);  in esdhc_readl_le()
550 		val |= FIELD_PREP(SDHCI_MAX_CURRENT_300_MASK, 0xFF);  in esdhc_readl_le()
551 		val |= FIELD_PREP(SDHCI_MAX_CURRENT_180_MASK, 0xFF);  in esdhc_readl_le()
631 	u16 ret = 0;  in esdhc_readw_le()
691 	u32 new_val = 0;  in esdhc_writew_le()
806 		val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);  in esdhc_writew_le()
809 	esdhc_clrset_le(host, 0xffff, val, reg);  in esdhc_writew_le()
835 	u32 new_val = 0;  in esdhc_writeb_le()
862 		mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);  in esdhc_writeb_le()
871 	esdhc_clrset_le(host, 0xff, val, reg);  in esdhc_writeb_le()
879 			 * register bits [0..2] during the software reset. This  in esdhc_writeb_le()
884 			esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);  in esdhc_writeb_le()
896 				imx_data->is_ddr = 0;  in esdhc_writeb_le()
904 			esdhc_clrset_le(host, 0xff, new_val,  in esdhc_writeb_le()
943 	if (clock == 0) {  in esdhc_pltfm_set_clock()
944 		host->mmc->actual_clock = 0;  in esdhc_pltfm_set_clock()
948 	/* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */  in esdhc_pltfm_set_clock()
1041 		ctrl = 0;  in esdhc_pltfm_set_bus_width()
1064 			writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);  in esdhc_reset_tuning()
1108 		return 0;  in usdhc_execute_tuning()
1134 	esdhc_clrset_le(host, 0xff, SDHCI_RESET_ALL, SDHCI_SOFTWARE_RESET);  in esdhc_prepare_tuning()
1147 		"tuning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",  in esdhc_prepare_tuning()
1171 	target_win_length = 0;  in esdhc_executing_tuning()
1210 	dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n",  in esdhc_executing_tuning()
1288 	writel(0, host->ioaddr + ESDHC_STROBE_DLL_CTRL);  in esdhc_set_strobe_dll()
1321 	imx_data->is_ddr = 0;  in esdhc_set_uhs_signaling()
1388 			esdhc_is_usdhc(imx_data) ? 0xF : 0xE,  in esdhc_set_timeout()
1394 	int cmd_error = 0;  in esdhc_cqhci_irq()
1395 	int data_error = 0;  in esdhc_cqhci_irq()
1402 	return 0;  in esdhc_cqhci_irq()
1467 			writel(readl(host->ioaddr + 0x6c) & ~BIT(7),  in sdhci_esdhc_imx_hwinit()
1468 				host->ioaddr + 0x6c);  in sdhci_esdhc_imx_hwinit()
1472 		writel(0x0, host->ioaddr + ESDHC_DLL_CTRL);  in sdhci_esdhc_imx_hwinit()
1569 		if (count-- == 0) {  in esdhc_cqe_enable()
1595 	cqhci_writel(cq_host, 0, CQHCI_CTL);  in esdhc_cqe_enable()
1645 		boarddata->delay_line = 0;  in sdhci_esdhc_imx_probe_dt()
1665 	if (mmc_gpio_get_cd(host->mmc) >= 0)  in sdhci_esdhc_imx_probe_dt()
1668 	return 0;  in sdhci_esdhc_imx_probe_dt()
1691 		cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0);  in sdhci_esdhc_imx_probe()
1745 		writel(0x0, host->ioaddr + ESDHC_MIX_CTRL);  in sdhci_esdhc_imx_probe()
1746 		writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS);  in sdhci_esdhc_imx_probe()
1747 		writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);  in sdhci_esdhc_imx_probe()
1821 	return 0;  in sdhci_esdhc_imx_probe()
1844 	dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);  in sdhci_esdhc_imx_remove()
1944 	esdhc_pltfm_set_clock(host, 0);  in sdhci_esdhc_runtime_suspend()
1963 		cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0);  in sdhci_esdhc_runtime_resume()
1982 	err = sdhci_runtime_resume_host(host, 0);  in sdhci_esdhc_runtime_resume()