Lines Matching +full:supports +full:- +full:cqe
1 // SPDX-License-Identifier: GPL-2.0-only
3 * sdhci-brcmstb.c Support for SDHCI on Broadcom BRCMSTB SoC's
16 #include "sdhci-cqhci.h"
17 #include "sdhci-pltfm.h"
69 if (!(priv->flags & BRCMSTB_PRIV_FLAGS_GATE_CLOCK)) in enable_clock_gating()
81 /* Reset will clear this, so re-enable it */ in brcmstb_reset()
94 * bits, hence access SDHCI_CLOCK_CONTROL register as 32-bit register in brcmstb_sdhci_reset_cmd_data()
108 mmc_hostname(host->mmc), (int)mask); in brcmstb_sdhci_reset_cmd_data()
124 /* Reset will clear this, so re-enable it */ in brcmstb_reset_74165b0()
134 dev_dbg(mmc_dev(mmc), "%s(): Setting HS400-Enhanced-Strobe mode\n", in sdhci_brcmstb_hs400es()
136 reg = readl(host->ioaddr + SDHCI_VENDOR); in sdhci_brcmstb_hs400es()
137 if (ios->enhanced_strobe) in sdhci_brcmstb_hs400es()
141 writel(reg, host->ioaddr + SDHCI_VENDOR); in sdhci_brcmstb_hs400es()
148 host->mmc->actual_clock = 0; in sdhci_brcmstb_set_clock()
150 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); in sdhci_brcmstb_set_clock()
164 dev_dbg(mmc_dev(host->mmc), "%s: Setting UHS signaling for %d timing\n", in sdhci_brcmstb_set_uhs_signaling()
184 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */ in sdhci_brcmstb_set_uhs_signaling()
198 if ((host->mmc->caps & MMC_CAP_UHS_I_SDR_MASK) || (host->mmc->caps2 & MMC_CAP_HSE_MASK)) { in sdhci_brcmstb_cfginit_2712()
199 reg = readl(brcmstb_priv->cfg_regs + SDIO_CFG_MAX_50MHZ_MODE); in sdhci_brcmstb_cfginit_2712()
202 writel(reg, brcmstb_priv->cfg_regs + SDIO_CFG_MAX_50MHZ_MODE); in sdhci_brcmstb_cfginit_2712()
205 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) || in sdhci_brcmstb_cfginit_2712()
206 (host->mmc->caps & MMC_CAP_NEEDS_POLL)) { in sdhci_brcmstb_cfginit_2712()
208 reg = readl(brcmstb_priv->cfg_regs + SDIO_CFG_CTRL); in sdhci_brcmstb_cfginit_2712()
211 writel(reg, brcmstb_priv->cfg_regs + SDIO_CFG_CTRL); in sdhci_brcmstb_cfginit_2712()
298 { .compatible = "brcm,bcm2712-sdhci", .data = &match_priv_2712 },
299 { .compatible = "brcm,bcm7425-sdhci", .data = &match_priv_7425 },
300 { .compatible = "brcm,bcm7445-sdhci", .data = &match_priv_7445 },
301 { .compatible = "brcm,bcm7216-sdhci", .data = &match_priv_7216 },
302 { .compatible = "brcm,bcm74165b0-sdhci", .data = &match_priv_74165b0 },
314 cqhci_irq(host->mmc, intmask, cmd_error, data_error); in sdhci_brcmstb_cqhci_irq()
326 if ((priv->flags & BRCMSTB_PRIV_FLAGS_HAS_CQE) == 0) in sdhci_brcmstb_add_host()
329 dev_dbg(mmc_dev(host->mmc), "CQE is enabled\n"); in sdhci_brcmstb_add_host()
330 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; in sdhci_brcmstb_add_host()
335 cq_host = devm_kzalloc(mmc_dev(host->mmc), in sdhci_brcmstb_add_host()
338 ret = -ENOMEM; in sdhci_brcmstb_add_host()
342 cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR; in sdhci_brcmstb_add_host()
343 cq_host->ops = &sdhci_brcmstb_cqhci_ops; in sdhci_brcmstb_add_host()
345 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; in sdhci_brcmstb_add_host()
347 dev_dbg(mmc_dev(host->mmc), "Using 64 bit DMA\n"); in sdhci_brcmstb_add_host()
348 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; in sdhci_brcmstb_add_host()
351 ret = cqhci_init(cq_host, host->mmc, dma64); in sdhci_brcmstb_add_host()
379 match = of_match_node(sdhci_brcm_of_match, pdev->dev.of_node); in sdhci_brcmstb_probe()
380 match_priv = match->data; in sdhci_brcmstb_probe()
382 dev_dbg(&pdev->dev, "Probe found match for %s\n", match->compatible); in sdhci_brcmstb_probe()
384 clk = devm_clk_get_optional_enabled(&pdev->dev, NULL); in sdhci_brcmstb_probe()
386 return dev_err_probe(&pdev->dev, PTR_ERR(clk), in sdhci_brcmstb_probe()
390 brcmstb_pdata.ops = match_priv->ops; in sdhci_brcmstb_probe()
398 if (device_property_read_bool(&pdev->dev, "supports-cqe")) { in sdhci_brcmstb_probe()
399 priv->flags |= BRCMSTB_PRIV_FLAGS_HAS_CQE; in sdhci_brcmstb_probe()
400 match_priv->ops->irq = sdhci_brcmstb_cqhci_irq; in sdhci_brcmstb_probe()
403 /* Map in the non-standard CFG registers */ in sdhci_brcmstb_probe()
404 priv->cfg_regs = devm_platform_get_and_ioremap_resource(pdev, 1, NULL); in sdhci_brcmstb_probe()
405 if (IS_ERR(priv->cfg_regs)) { in sdhci_brcmstb_probe()
406 res = PTR_ERR(priv->cfg_regs); in sdhci_brcmstb_probe()
411 res = mmc_of_parse(host->mmc); in sdhci_brcmstb_probe()
417 * voltage switch so only enable it for non-removable devices. in sdhci_brcmstb_probe()
419 if ((match_priv->flags & BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE) && in sdhci_brcmstb_probe()
420 (host->mmc->caps & MMC_CAP_NONREMOVABLE)) in sdhci_brcmstb_probe()
421 priv->flags |= BRCMSTB_PRIV_FLAGS_GATE_CLOCK; in sdhci_brcmstb_probe()
427 if (match_priv->hs400es && in sdhci_brcmstb_probe()
428 (host->mmc->caps2 & MMC_CAP2_HS400_ES)) in sdhci_brcmstb_probe()
429 host->mmc_host_ops.hs400_enhanced_strobe = match_priv->hs400es; in sdhci_brcmstb_probe()
431 if (match_priv->cfginit) in sdhci_brcmstb_probe()
432 match_priv->cfginit(host); in sdhci_brcmstb_probe()
440 if (match_priv->flags & BRCMSTB_MATCH_FLAGS_NO_64BIT) in sdhci_brcmstb_probe()
441 host->caps &= ~SDHCI_CAN_64BIT; in sdhci_brcmstb_probe()
442 host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 | in sdhci_brcmstb_probe()
445 if (match_priv->flags & BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT) in sdhci_brcmstb_probe()
446 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; in sdhci_brcmstb_probe()
448 if (!(match_priv->flags & BRCMSTB_MATCH_FLAGS_USE_CARD_BUSY)) in sdhci_brcmstb_probe()
449 host->mmc_host_ops.card_busy = NULL; in sdhci_brcmstb_probe()
452 if (device_property_read_u32(&pdev->dev, "clock-frequency", in sdhci_brcmstb_probe()
453 &priv->base_freq_hz) != 0) in sdhci_brcmstb_probe()
456 base_clk = devm_clk_get_optional(&pdev->dev, "sdio_freq"); in sdhci_brcmstb_probe()
458 dev_warn(&pdev->dev, "Clock for \"sdio_freq\" not found\n"); in sdhci_brcmstb_probe()
467 clk_set_rate(base_clk, priv->base_freq_hz); in sdhci_brcmstb_probe()
470 host->caps &= ~SDHCI_CLOCK_V3_BASE_MASK; in sdhci_brcmstb_probe()
471 host->caps |= (actual_clock_mhz << SDHCI_CLOCK_BASE_SHIFT); in sdhci_brcmstb_probe()
473 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; in sdhci_brcmstb_probe()
475 dev_dbg(&pdev->dev, "Base Clock Frequency changed to %dMHz\n", in sdhci_brcmstb_probe()
477 priv->base_clk = base_clk; in sdhci_brcmstb_probe()
484 pltfm_host->clk = clk; in sdhci_brcmstb_probe()
495 sdhci_pltfm_suspend(&pdev->dev); in sdhci_brcmstb_shutdown()
507 clk_disable_unprepare(priv->base_clk); in sdhci_brcmstb_suspend()
519 if (!ret && priv->base_freq_hz) { in sdhci_brcmstb_resume()
520 ret = clk_prepare_enable(priv->base_clk); in sdhci_brcmstb_resume()
528 (clk_get_rate(priv->base_clk) != priv->base_freq_hz)) in sdhci_brcmstb_resume()
529 ret = clk_set_rate(priv->base_clk, priv->base_freq_hz); in sdhci_brcmstb_resume()
542 .name = "sdhci-brcmstb",