Lines Matching +full:phase +full:- +full:shift
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Modified from dw_mmc-hi3798cv200.c
18 #include "dw_mmc-pltfm.h"
38 struct dw_mci_hi3798mv200_priv *priv = host->priv; in dw_mci_hi3798mv200_set_ios()
39 struct mmc_clk_phase phase = priv->phase_map.phase[ios->timing]; in dw_mci_hi3798mv200_set_ios() local
43 if (ios->timing == MMC_TIMING_MMC_DDR52 in dw_mci_hi3798mv200_set_ios()
44 || ios->timing == MMC_TIMING_UHS_DDR50) in dw_mci_hi3798mv200_set_ios()
51 if (ios->timing == MMC_TIMING_MMC_HS400) in dw_mci_hi3798mv200_set_ios()
57 if (clk_set_rate(host->ciu_clk, ios->clock)) in dw_mci_hi3798mv200_set_ios()
58 dev_warn(host->dev, "Failed to set rate to %u\n", ios->clock); in dw_mci_hi3798mv200_set_ios()
65 host->bus_hz = clk_get_rate(host->ciu_clk); in dw_mci_hi3798mv200_set_ios()
67 if (phase.valid) { in dw_mci_hi3798mv200_set_ios()
68 clk_set_phase(priv->drive_clk, phase.out_deg); in dw_mci_hi3798mv200_set_ios()
69 clk_set_phase(priv->sample_clk, phase.in_deg); in dw_mci_hi3798mv200_set_ios()
71 dev_warn(host->dev, in dw_mci_hi3798mv200_set_ios()
72 "The phase entry for timing mode %d is missing in device tree.\n", in dw_mci_hi3798mv200_set_ios()
73 ios->timing); in dw_mci_hi3798mv200_set_ios()
79 struct dw_mci_hi3798mv200_priv *priv = slot->host->priv; in dw_mci_hi3798mv200_enable_tuning()
81 return regmap_clear_bits(priv->crg_reg, priv->sap_dll_offset, SAP_DLL_CTRL_DLLMODE); in dw_mci_hi3798mv200_enable_tuning()
86 struct dw_mci_hi3798mv200_priv *priv = slot->host->priv; in dw_mci_hi3798mv200_disable_tuning()
88 return regmap_set_bits(priv->crg_reg, priv->sap_dll_offset, SAP_DLL_CTRL_DLLMODE); in dw_mci_hi3798mv200_disable_tuning()
95 struct dw_mci *host = slot->host; in dw_mci_hi3798mv200_execute_tuning_mix_mode()
96 struct dw_mci_hi3798mv200_priv *priv = host->priv; in dw_mci_hi3798mv200_execute_tuning_mix_mode()
97 int raise_point = -1, fall_point = -1, mid; in dw_mci_hi3798mv200_execute_tuning_mix_mode()
98 int err, prev_err = -1; in dw_mci_hi3798mv200_execute_tuning_mix_mode()
109 clk_set_phase(priv->sample_clk, degrees[i]); in dw_mci_hi3798mv200_execute_tuning_mix_mode()
118 err = mmc_send_tuning(slot->mmc, opcode, NULL); in dw_mci_hi3798mv200_execute_tuning_mix_mode()
127 fall_point = i - 1; in dw_mci_hi3798mv200_execute_tuning_mix_mode()
132 if (raise_point != -1 && fall_point != -1) in dw_mci_hi3798mv200_execute_tuning_mix_mode()
144 if (raise_point == -1) in dw_mci_hi3798mv200_execute_tuning_mix_mode()
146 if (fall_point == -1) in dw_mci_hi3798mv200_execute_tuning_mix_mode()
147 fall_point = ARRAY_SIZE(degrees) - 1; in dw_mci_hi3798mv200_execute_tuning_mix_mode()
150 (ARRAY_SIZE(degrees) - 1)) in dw_mci_hi3798mv200_execute_tuning_mix_mode()
153 mid = (raise_point + ARRAY_SIZE(degrees) - 1) / 2; in dw_mci_hi3798mv200_execute_tuning_mix_mode()
160 * simply use the same phase for all timing needs tuning. in dw_mci_hi3798mv200_execute_tuning_mix_mode()
162 priv->phase_map.phase[MMC_TIMING_MMC_HS200].in_deg = degrees[mid]; in dw_mci_hi3798mv200_execute_tuning_mix_mode()
163 priv->phase_map.phase[MMC_TIMING_MMC_HS400].in_deg = degrees[mid]; in dw_mci_hi3798mv200_execute_tuning_mix_mode()
164 priv->phase_map.phase[MMC_TIMING_UHS_SDR104].in_deg = degrees[mid]; in dw_mci_hi3798mv200_execute_tuning_mix_mode()
166 clk_set_phase(priv->sample_clk, degrees[mid]); in dw_mci_hi3798mv200_execute_tuning_mix_mode()
167 dev_dbg(host->dev, "Tuning clk_sample[%d, %d], set[%d]\n", in dw_mci_hi3798mv200_execute_tuning_mix_mode()
171 dev_err(host->dev, "No valid clk_sample shift!\n"); in dw_mci_hi3798mv200_execute_tuning_mix_mode()
172 ret = -EINVAL; in dw_mci_hi3798mv200_execute_tuning_mix_mode()
183 struct device_node *np = host->dev->of_node; in dw_mci_hi3798mv200_init()
186 priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL); in dw_mci_hi3798mv200_init()
188 return -ENOMEM; in dw_mci_hi3798mv200_init()
190 mmc_of_parse_clk_phase(host->dev, &priv->phase_map); in dw_mci_hi3798mv200_init()
192 priv->sample_clk = devm_clk_get_enabled(host->dev, "ciu-sample"); in dw_mci_hi3798mv200_init()
193 if (IS_ERR(priv->sample_clk)) in dw_mci_hi3798mv200_init()
194 return dev_err_probe(host->dev, PTR_ERR(priv->sample_clk), in dw_mci_hi3798mv200_init()
195 "failed to get enabled ciu-sample clock\n"); in dw_mci_hi3798mv200_init()
197 priv->drive_clk = devm_clk_get_enabled(host->dev, "ciu-drive"); in dw_mci_hi3798mv200_init()
198 if (IS_ERR(priv->drive_clk)) in dw_mci_hi3798mv200_init()
199 return dev_err_probe(host->dev, PTR_ERR(priv->drive_clk), in dw_mci_hi3798mv200_init()
200 "failed to get enabled ciu-drive clock\n"); in dw_mci_hi3798mv200_init()
202 priv->crg_reg = syscon_regmap_lookup_by_phandle(np, "hisilicon,sap-dll-reg"); in dw_mci_hi3798mv200_init()
203 if (IS_ERR(priv->crg_reg)) in dw_mci_hi3798mv200_init()
204 return dev_err_probe(host->dev, PTR_ERR(priv->crg_reg), in dw_mci_hi3798mv200_init()
207 ret = of_property_read_u32_index(np, "hisilicon,sap-dll-reg", 1, &priv->sap_dll_offset); in dw_mci_hi3798mv200_init()
209 return dev_err_probe(host->dev, ret, "failed to get sample DLL register offset\n"); in dw_mci_hi3798mv200_init()
211 host->priv = priv; in dw_mci_hi3798mv200_init()
223 { .compatible = "hisilicon,hi3798mv200-dw-mshc" },
249 MODULE_DESCRIPTION("HiSilicon Hi3798MV200 Specific DW-MSHC Driver Extension");