1 // SPDX-License-Identifier: GPL-2.0
17 #include "dw_mmc-pltfm.h"
28 	struct hi3798cv200_priv *priv = host->priv;  in dw_mci_hi3798cv200_set_ios()
32 	if (ios->timing == MMC_TIMING_MMC_DDR52 ||  in dw_mci_hi3798cv200_set_ios()
33 	    ios->timing == MMC_TIMING_UHS_DDR50)  in dw_mci_hi3798cv200_set_ios()
40 	if (ios->timing == MMC_TIMING_MMC_DDR52)  in dw_mci_hi3798cv200_set_ios()
47 	if (ios->timing == MMC_TIMING_MMC_HS400)  in dw_mci_hi3798cv200_set_ios()
53 	if (ios->timing == MMC_TIMING_MMC_HS ||  in dw_mci_hi3798cv200_set_ios()
54 	    ios->timing == MMC_TIMING_LEGACY)  in dw_mci_hi3798cv200_set_ios()
55 		clk_set_phase(priv->drive_clk, 180);  in dw_mci_hi3798cv200_set_ios()
56 	else if (ios->timing == MMC_TIMING_MMC_HS200)  in dw_mci_hi3798cv200_set_ios()
57 		clk_set_phase(priv->drive_clk, 135);  in dw_mci_hi3798cv200_set_ios()
64 	struct dw_mci *host = slot->host;  in dw_mci_hi3798cv200_execute_tuning()
65 	struct hi3798cv200_priv *priv = host->priv;  in dw_mci_hi3798cv200_execute_tuning()
66 	int raise_point = -1, fall_point = -1;  in dw_mci_hi3798cv200_execute_tuning()
67 	int err, prev_err = -1;  in dw_mci_hi3798cv200_execute_tuning()
72 		clk_set_phase(priv->sample_clk, degrees[i]);  in dw_mci_hi3798cv200_execute_tuning()
75 		err = mmc_send_tuning(slot->mmc, opcode, NULL);  in dw_mci_hi3798cv200_execute_tuning()
81 				fall_point = i - 1;  in dw_mci_hi3798cv200_execute_tuning()
86 		if (raise_point != -1 && fall_point != -1)  in dw_mci_hi3798cv200_execute_tuning()
94 		if (raise_point == -1)  in dw_mci_hi3798cv200_execute_tuning()
96 		if (fall_point == -1)  in dw_mci_hi3798cv200_execute_tuning()
97 			fall_point = ARRAY_SIZE(degrees) - 1;  in dw_mci_hi3798cv200_execute_tuning()
100 			    (ARRAY_SIZE(degrees) - 1))  in dw_mci_hi3798cv200_execute_tuning()
103 				i = (raise_point + ARRAY_SIZE(degrees) - 1) / 2;  in dw_mci_hi3798cv200_execute_tuning()
108 		clk_set_phase(priv->sample_clk, degrees[i]);  in dw_mci_hi3798cv200_execute_tuning()
109 		dev_dbg(host->dev, "Tuning clk_sample[%d, %d], set[%d]\n",  in dw_mci_hi3798cv200_execute_tuning()
112 		dev_err(host->dev, "No valid clk_sample shift! use default\n");  in dw_mci_hi3798cv200_execute_tuning()
113 		err = -EINVAL;  in dw_mci_hi3798cv200_execute_tuning()
125 	priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);  in dw_mci_hi3798cv200_init()
127 		return -ENOMEM;  in dw_mci_hi3798cv200_init()
129 	priv->sample_clk = devm_clk_get(host->dev, "ciu-sample");  in dw_mci_hi3798cv200_init()
130 	if (IS_ERR(priv->sample_clk)) {  in dw_mci_hi3798cv200_init()
131 		dev_err(host->dev, "failed to get ciu-sample clock\n");  in dw_mci_hi3798cv200_init()
132 		return PTR_ERR(priv->sample_clk);  in dw_mci_hi3798cv200_init()
135 	priv->drive_clk = devm_clk_get(host->dev, "ciu-drive");  in dw_mci_hi3798cv200_init()
136 	if (IS_ERR(priv->drive_clk)) {  in dw_mci_hi3798cv200_init()
137 		dev_err(host->dev, "failed to get ciu-drive clock\n");  in dw_mci_hi3798cv200_init()
138 		return PTR_ERR(priv->drive_clk);  in dw_mci_hi3798cv200_init()
141 	ret = clk_prepare_enable(priv->sample_clk);  in dw_mci_hi3798cv200_init()
143 		dev_err(host->dev, "failed to enable ciu-sample clock\n");  in dw_mci_hi3798cv200_init()
147 	ret = clk_prepare_enable(priv->drive_clk);  in dw_mci_hi3798cv200_init()
149 		dev_err(host->dev, "failed to enable ciu-drive clock\n");  in dw_mci_hi3798cv200_init()
153 	host->priv = priv;  in dw_mci_hi3798cv200_init()
157 	clk_disable_unprepare(priv->sample_clk);  in dw_mci_hi3798cv200_init()
176 	struct hi3798cv200_priv *priv = host->priv;  in dw_mci_hi3798cv200_remove()
178 	clk_disable_unprepare(priv->drive_clk);  in dw_mci_hi3798cv200_remove()
179 	clk_disable_unprepare(priv->sample_clk);  in dw_mci_hi3798cv200_remove()
185 	{ .compatible = "hisilicon,hi3798cv200-dw-mshc", },
201 MODULE_DESCRIPTION("HiSilicon Hi3798CV200 Specific DW-MSHC Driver Extension");