Lines Matching +full:supports +full:- +full:cqe
1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/blk-crypto.h>
9 #include <linux/blk-crypto-profile.h>
12 #include "cqhci-crypto.h"
14 /* Map from blk-crypto modes to CQHCI crypto algorithm IDs and key sizes */
31 return mmc->cqe_private; in cqhci_host_from_crypto_profile()
38 u32 slot_offset = cq_host->crypto_cfg_register + slot * sizeof(*cfg); in cqhci_crypto_program_key()
41 if (cq_host->ops->program_key) in cqhci_crypto_program_key()
42 return cq_host->ops->program_key(cq_host, cfg, slot); in cqhci_crypto_program_key()
45 cqhci_writel(cq_host, 0, slot_offset + 16 * sizeof(cfg->reg_val[0])); in cqhci_crypto_program_key()
49 cqhci_writel(cq_host, le32_to_cpu(cfg->reg_val[i]), in cqhci_crypto_program_key()
50 slot_offset + i * sizeof(cfg->reg_val[0])); in cqhci_crypto_program_key()
53 cqhci_writel(cq_host, le32_to_cpu(cfg->reg_val[17]), in cqhci_crypto_program_key()
54 slot_offset + 17 * sizeof(cfg->reg_val[0])); in cqhci_crypto_program_key()
56 cqhci_writel(cq_host, le32_to_cpu(cfg->reg_val[16]), in cqhci_crypto_program_key()
57 slot_offset + 16 * sizeof(cfg->reg_val[0])); in cqhci_crypto_program_key()
68 cq_host->crypto_cap_array; in cqhci_crypto_keyslot_program()
70 &cqhci_crypto_algs[key->crypto_cfg.crypto_mode]; in cqhci_crypto_keyslot_program()
71 u8 data_unit_mask = key->crypto_cfg.data_unit_size / 512; in cqhci_crypto_keyslot_program()
73 int cap_idx = -1; in cqhci_crypto_keyslot_program()
78 for (i = 0; i < cq_host->crypto_capabilities.num_crypto_cap; i++) { in cqhci_crypto_keyslot_program()
79 if (ccap_array[i].algorithm_id == alg->alg && in cqhci_crypto_keyslot_program()
80 ccap_array[i].key_size == alg->key_size && in cqhci_crypto_keyslot_program()
87 return -EOPNOTSUPP; in cqhci_crypto_keyslot_program()
95 memcpy(cfg.crypto_key, key->raw, key->size/2); in cqhci_crypto_keyslot_program()
97 key->raw + key->size/2, key->size/2); in cqhci_crypto_keyslot_program()
99 memcpy(cfg.crypto_key, key->raw, key->size); in cqhci_crypto_keyslot_program()
132 * controller is runtime-suspended. However, the CQE won't necessarily be
156 * cqhci_crypto_init - initialize CQHCI crypto support
159 * If the driver previously set MMC_CAP2_CRYPTO and the CQE declares
162 * all keyslots, and enabling 128-bit task descriptors.
170 struct mmc_host *mmc = cq_host->mmc; in cqhci_crypto_init()
172 struct blk_crypto_profile *profile = &mmc->crypto_profile; in cqhci_crypto_init()
179 if (!(mmc->caps2 & MMC_CAP2_CRYPTO) || in cqhci_crypto_init()
183 cq_host->crypto_capabilities.reg_val = in cqhci_crypto_init()
186 cq_host->crypto_cfg_register = in cqhci_crypto_init()
187 (u32)cq_host->crypto_capabilities.config_array_ptr * 0x100; in cqhci_crypto_init()
189 cq_host->crypto_cap_array = in cqhci_crypto_init()
190 devm_kcalloc(dev, cq_host->crypto_capabilities.num_crypto_cap, in cqhci_crypto_init()
191 sizeof(cq_host->crypto_cap_array[0]), GFP_KERNEL); in cqhci_crypto_init()
192 if (!cq_host->crypto_cap_array) { in cqhci_crypto_init()
193 err = -ENOMEM; in cqhci_crypto_init()
201 num_keyslots = cq_host->crypto_capabilities.config_count + 1; in cqhci_crypto_init()
207 profile->ll_ops = cqhci_crypto_ops; in cqhci_crypto_init()
208 profile->dev = dev; in cqhci_crypto_init()
210 /* Unfortunately, CQHCI crypto only supports 32 DUN bits. */ in cqhci_crypto_init()
211 profile->max_dun_bytes_supported = 4; in cqhci_crypto_init()
217 for (cap_idx = 0; cap_idx < cq_host->crypto_capabilities.num_crypto_cap; in cqhci_crypto_init()
219 cq_host->crypto_cap_array[cap_idx].reg_val = in cqhci_crypto_init()
224 cq_host->crypto_cap_array[cap_idx]); in cqhci_crypto_init()
227 profile->modes_supported[blk_mode_num] |= in cqhci_crypto_init()
228 cq_host->crypto_cap_array[cap_idx].sdus_mask * 512; in cqhci_crypto_init()
235 /* CQHCI crypto requires the use of 128-bit task descriptors. */ in cqhci_crypto_init()
236 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; in cqhci_crypto_init()
241 mmc->caps2 &= ~MMC_CAP2_CRYPTO; in cqhci_crypto_init()