Lines Matching refs:bw_ext_csd
708 u8 *bw_ext_csd; in mmc_compare_ext_csds() local
714 err = mmc_get_ext_csd(card, &bw_ext_csd); in mmc_compare_ext_csds()
720 bw_ext_csd[EXT_CSD_PARTITION_SUPPORT]) && in mmc_compare_ext_csds()
722 bw_ext_csd[EXT_CSD_ERASED_MEM_CONT]) && in mmc_compare_ext_csds()
724 bw_ext_csd[EXT_CSD_REV]) && in mmc_compare_ext_csds()
726 bw_ext_csd[EXT_CSD_STRUCTURE]) && in mmc_compare_ext_csds()
728 bw_ext_csd[EXT_CSD_CARD_TYPE]) && in mmc_compare_ext_csds()
730 bw_ext_csd[EXT_CSD_S_A_TIMEOUT]) && in mmc_compare_ext_csds()
732 bw_ext_csd[EXT_CSD_HC_WP_GRP_SIZE]) && in mmc_compare_ext_csds()
734 bw_ext_csd[EXT_CSD_ERASE_TIMEOUT_MULT]) && in mmc_compare_ext_csds()
736 bw_ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]) && in mmc_compare_ext_csds()
738 bw_ext_csd[EXT_CSD_SEC_TRIM_MULT]) && in mmc_compare_ext_csds()
740 bw_ext_csd[EXT_CSD_SEC_ERASE_MULT]) && in mmc_compare_ext_csds()
742 bw_ext_csd[EXT_CSD_SEC_FEATURE_SUPPORT]) && in mmc_compare_ext_csds()
744 bw_ext_csd[EXT_CSD_TRIM_MULT]) && in mmc_compare_ext_csds()
746 bw_ext_csd[EXT_CSD_SEC_CNT + 0]) && in mmc_compare_ext_csds()
748 bw_ext_csd[EXT_CSD_SEC_CNT + 1]) && in mmc_compare_ext_csds()
750 bw_ext_csd[EXT_CSD_SEC_CNT + 2]) && in mmc_compare_ext_csds()
752 bw_ext_csd[EXT_CSD_SEC_CNT + 3]) && in mmc_compare_ext_csds()
754 bw_ext_csd[EXT_CSD_PWR_CL_52_195]) && in mmc_compare_ext_csds()
756 bw_ext_csd[EXT_CSD_PWR_CL_26_195]) && in mmc_compare_ext_csds()
758 bw_ext_csd[EXT_CSD_PWR_CL_52_360]) && in mmc_compare_ext_csds()
760 bw_ext_csd[EXT_CSD_PWR_CL_26_360]) && in mmc_compare_ext_csds()
762 bw_ext_csd[EXT_CSD_PWR_CL_200_195]) && in mmc_compare_ext_csds()
764 bw_ext_csd[EXT_CSD_PWR_CL_200_360]) && in mmc_compare_ext_csds()
766 bw_ext_csd[EXT_CSD_PWR_CL_DDR_52_195]) && in mmc_compare_ext_csds()
768 bw_ext_csd[EXT_CSD_PWR_CL_DDR_52_360]) && in mmc_compare_ext_csds()
770 bw_ext_csd[EXT_CSD_PWR_CL_DDR_200_360])); in mmc_compare_ext_csds()
775 kfree(bw_ext_csd); in mmc_compare_ext_csds()