34 #define XSDFEC_CODE_WR_PROTECT_ADDR (0x4)
37 #define XSDFEC_ACTIVE_ADDR (0x8)
38 #define XSDFEC_IS_ACTIVITY_SET (0x1)
41 #define XSDFEC_AXIS_WIDTH_ADDR (0xC)
45 #define XSDFEC_AXIS_DIN_WIDTH_LSB (0)
48 #define XSDFEC_AXIS_ENABLE_ADDR (0x10)
49 #define XSDFEC_AXIS_OUT_ENABLE_MASK (0x38)
50 #define XSDFEC_AXIS_IN_ENABLE_MASK (0x7)
55 #define XSDFEC_FEC_CODE_ADDR (0x14)
58 #define XSDFEC_ORDER_ADDR (0x18)
61 #define XSDFEC_ISR_ADDR (0x1C)
63 #define XSDFEC_ISR_MASK (0x3F)
66 #define XSDFEC_IER_ADDR (0x20)
68 #define XSDFEC_IDR_ADDR (0x24)
70 #define XSDFEC_IMR_ADDR (0x28)
73 #define XSDFEC_ECC_ISR_ADDR (0x2C)
75 #define XSDFEC_ECC_ISR_SBE_MASK (0x7FF)
77 #define XSDFEC_PL_INIT_ECC_ISR_SBE_MASK (0x3C00000)
79 #define XSDFEC_ECC_ISR_MBE_MASK (0x3FF800)
81 #define XSDFEC_PL_INIT_ECC_ISR_MBE_MASK (0x3C000000)
102 #define XSDFEC_ECC_IER_ADDR (0x30)
104 #define XSDFEC_ECC_IDR_ADDR (0x34)
106 #define XSDFEC_ECC_IMR_ADDR (0x38)
109 #define XSDFEC_BYPASS_ADDR (0x3C)
112 #define XSDFEC_TURBO_ADDR (0x100)
113 #define XSDFEC_TURBO_SCALE_MASK (0xFFF)
118 #define XSDFEC_LDPC_CODE_REG0_ADDR_BASE (0x2000)
119 #define XSDFEC_LDPC_CODE_REG0_ADDR_HIGH (0x27F0)
123 #define XSDFEC_REG0_N_LSB (0)
130 #define XSDFEC_LDPC_CODE_REG1_ADDR_BASE (0x2004)
131 #define XSDFEC_LDPC_CODE_REG1_ADDR_HIGH (0x27f4)
134 #define XSDFEC_REG1_NO_PACKING_MASK (0x400)
136 #define XSDFEC_REG1_NM_MASK (0xFF800)
138 #define XSDFEC_REG1_BYPASS_MASK (0x100000)
141 #define XSDFEC_LDPC_CODE_REG2_ADDR_BASE (0x2008)
142 #define XSDFEC_LDPC_CODE_REG2_ADDR_HIGH (0x27f8)
145 #define XSDFEC_REG2_NNMQC_MASK (0xFFE00)
147 #define XSDFEC_REG2_NORM_TYPE_MASK (0x100000)
149 #define XSDFEC_REG2_SPECIAL_QC_MASK (0x200000)
151 #define XSDFEC_REG2_NO_FINAL_PARITY_MASK (0x400000)
153 #define XSDFEC_REG2_MAX_SCHEDULE_MASK (0x1800000)
157 #define XSDFEC_LDPC_CODE_REG3_ADDR_BASE (0x200C)
158 #define XSDFEC_LDPC_CODE_REG3_ADDR_HIGH (0x27FC)
162 #define XSDFEC_LDPC_REG_JUMP (0x10)
238 	dev_dbg(xsdfec->dev, "Writing 0x%x to offset 0x%x", value, addr);  in xsdfec_regwrite()
247 	dev_dbg(xsdfec->dev, "Read value = 0x%x from offset 0x%x", rval, addr);  in xsdfec_regread()
259 	*config_value = (reg_val & bit_mask) > 0;  in update_bool_config_from_reg()
272 				    0, /* Bit Number, maybe change to mask */  in update_config_from_hw()
276 				    0, /* Bit Number */  in update_config_from_hw()
280 	xsdfec->config.irq.enable_isr = (reg_value & XSDFEC_ISR_MASK) > 0;  in update_config_from_hw()
284 		(reg_value & XSDFEC_ECC_ISR_MASK) > 0;  in update_config_from_hw()
287 	sdfec_started = (reg_value & XSDFEC_AXIS_IN_ENABLE_MASK) > 0;  in update_config_from_hw()
299 	memset(&status, 0, sizeof(status));  in xsdfec_get_status()
348 	return 0;  in xsdfec_isr_enable()
379 	return 0;  in xsdfec_ecc_isr_enable()
403 	if (isr_err < 0 || ecc_err < 0)  in xsdfec_set_irq()
445 	memset(&turbo_params, 0, sizeof(turbo_params));  in xsdfec_get_turbo()
450 	turbo_params.alg = reg_value & 0x1;  in xsdfec_get_turbo()
464 	if (n < XSDFEC_REG0_N_MIN || n > XSDFEC_REG0_N_MAX || psize == 0 ||  in xsdfec_reg0_write()
465 	    (n > XSDFEC_REG0_N_MUL_P * psize) || n <= k || ((n % psize) != 0)) {  in xsdfec_reg0_write()
472 	    (k > XSDFEC_REG0_K_MUL_P * psize) || ((k % psize) != 0)) {  in xsdfec_reg0_write()
481 		dev_dbg(xsdfec->dev, "Writing outside of LDPC reg0 space 0x%x",  in xsdfec_reg0_write()
490 	return 0;  in xsdfec_reg0_write()
503 	if (no_packing != 0 && no_packing != 1)  in xsdfec_reg1_write()
515 		dev_dbg(xsdfec->dev, "Writing outside of LDPC reg1 space 0x%x",  in xsdfec_reg1_write()
524 	return 0;  in xsdfec_reg1_write()
568 		dev_dbg(xsdfec->dev, "Writing outside of LDPC reg2 space 0x%x",  in xsdfec_reg2_write()
577 	return 0;  in xsdfec_reg2_write()
589 		dev_dbg(xsdfec->dev, "Writing outside of LDPC reg3 space 0x%x",  in xsdfec_reg3_write()
598 	return 0;  in xsdfec_reg3_write()
605 	u32 reg = 0;  in xsdfec_table_write()
631 	res = pin_user_pages_fast((unsigned long)src_ptr, nr_pages, 0, pages);  in xsdfec_table_write()
633 		if (res > 0)  in xsdfec_table_write()
639 	for (i = 0; i < nr_pages; i++) {  in xsdfec_table_write()
652 	return 0;  in xsdfec_table_write()
680 	/* Write Reg 0 */  in xsdfec_add_ldpc()
714 	if (ret < 0)  in xsdfec_add_ldpc()
720 	if (ret < 0)  in xsdfec_add_ldpc()
754 	return 0;  in xsdfec_set_order()
773 		xsdfec_regwrite(xsdfec, XSDFEC_BYPASS_ADDR, 0);  in xsdfec_set_bypass()
777 	return 0;  in xsdfec_set_bypass()
799 	u32 axis_width_field = 0;  in xsdfec_translate_axis_width_cfg_val()
803 		axis_width_field = 0;  in xsdfec_translate_axis_width_cfg_val()
819 	u32 axis_words_field = 0;  in xsdfec_translate_axis_words_cfg_val()
823 		axis_words_field = 0;  in xsdfec_translate_axis_words_cfg_val()
856 	return 0;  in xsdfec_cfg_axi_streams()
864 	regread &= 0x1;  in xsdfec_start()
877 	return 0;  in xsdfec_start()
892 	return 0;  in xsdfec_stop()
898 	xsdfec->isr_err_count = 0;  in xsdfec_clear_stats()
899 	xsdfec->uecc_count = 0;  in xsdfec_clear_stats()
900 	xsdfec->cecc_count = 0;  in xsdfec_clear_stats()
903 	return 0;  in xsdfec_clear_stats()
932 	return 0;  in xsdfec_set_default_config()
1003 	__poll_t mask = 0;  in xsdfec_poll()
1041 	if (rval < 0)  in xsdfec_parse_of()
1053 	if (rval < 0)  in xsdfec_parse_of()
1062 	if (rval < 0)  in xsdfec_parse_of()
1078 	if (rval < 0)  in xsdfec_parse_of()
1087 	if (rval < 0)  in xsdfec_parse_of()
1106 	return 0;  in xsdfec_parse_of()
1366 	xsdfec->regs = devm_platform_ioremap_resource(pdev, 0);  in xsdfec_probe()
1372 	xsdfec->irq = platform_get_irq(pdev, 0);  in xsdfec_probe()
1373 	if (xsdfec->irq < 0) {  in xsdfec_probe()
1379 	if (err < 0)  in xsdfec_probe()
1393 		if (err < 0) {  in xsdfec_probe()
1400 	if (err < 0)  in xsdfec_probe()
1414 	return 0;  in xsdfec_probe()