Lines Matching +full:save +full:- +full:mac +full:- +full:address
1 // SPDX-License-Identifier: GPL-2.0-only
26 #define PCH_PHUB_MAC_START_ADDR_EG20T 0x14 /* MAC data area start address
28 #define PCH_PHUB_MAC_START_ADDR_ML7223 0x20C /* MAC data area start address
30 #define PCH_PHUB_ROM_START_ADDR_EG20T 0x80 /* ROM data area start address offset
32 #define PCH_PHUB_ROM_START_ADDR_ML7213 0x400 /* ROM data area start address
35 #define PCH_PHUB_ROM_START_ADDR_ML7223 0x400 /* ROM data area start address
47 /* CM-iTC */
58 #define PCI_DEVICE_ID_ROHM_ML7223_mPHUB 0x8012 /* for Bus-m */
59 #define PCI_DEVICE_ID_ROHM_ML7223_nPHUB 0x8002 /* for Bus-n */
65 #define PCH_WORD_ADDR_MASK (~((1 << 2) - 1))
67 /* Registers address offset */
86 * struct pch_phub_reg - PHUB register structure
101 * @pch_phub_base_address: Register base address
102 * @pch_phub_extrom_base_address: external rom base address
103 * @pch_mac_start_address: MAC address area start address
104 * @pch_opt_rom_start_address: Option ROM start address
105 * @ioh_type: Save IOH type
131 /* SROM SPEC for MAC address assignment offset */
137 * pch_phub_read_modify_write_reg() - Reading modifying and writing register
139 * @reg_addr_offset: Register offset address value.
147 void __iomem *reg_addr = chip->pch_phub_base_address + reg_addr_offset; in pch_phub_read_modify_write_reg()
151 /* pch_phub_save_reg_conf - saves register configuration */
157 void __iomem *p = chip->pch_phub_base_address; in pch_phub_save_reg_conf()
159 chip->phub_id_reg = ioread32(p + PCH_PHUB_ID_REG); in pch_phub_save_reg_conf()
160 chip->q_pri_val_reg = ioread32(p + PCH_PHUB_QUEUE_PRI_VAL_REG); in pch_phub_save_reg_conf()
161 chip->rc_q_maxsize_reg = ioread32(p + PCH_PHUB_RC_QUEUE_MAXSIZE_REG); in pch_phub_save_reg_conf()
162 chip->bri_q_maxsize_reg = ioread32(p + PCH_PHUB_BRI_QUEUE_MAXSIZE_REG); in pch_phub_save_reg_conf()
163 chip->comp_resp_timeout_reg = in pch_phub_save_reg_conf()
165 chip->bus_slave_control_reg = in pch_phub_save_reg_conf()
167 chip->deadlock_avoid_type_reg = in pch_phub_save_reg_conf()
169 chip->intpin_reg_wpermit_reg0 = in pch_phub_save_reg_conf()
171 chip->intpin_reg_wpermit_reg1 = in pch_phub_save_reg_conf()
173 chip->intpin_reg_wpermit_reg2 = in pch_phub_save_reg_conf()
175 chip->intpin_reg_wpermit_reg3 = in pch_phub_save_reg_conf()
177 dev_dbg(&pdev->dev, "%s : " in pch_phub_save_reg_conf()
178 "chip->phub_id_reg=%x, " in pch_phub_save_reg_conf()
179 "chip->q_pri_val_reg=%x, " in pch_phub_save_reg_conf()
180 "chip->rc_q_maxsize_reg=%x, " in pch_phub_save_reg_conf()
181 "chip->bri_q_maxsize_reg=%x, " in pch_phub_save_reg_conf()
182 "chip->comp_resp_timeout_reg=%x, " in pch_phub_save_reg_conf()
183 "chip->bus_slave_control_reg=%x, " in pch_phub_save_reg_conf()
184 "chip->deadlock_avoid_type_reg=%x, " in pch_phub_save_reg_conf()
185 "chip->intpin_reg_wpermit_reg0=%x, " in pch_phub_save_reg_conf()
186 "chip->intpin_reg_wpermit_reg1=%x, " in pch_phub_save_reg_conf()
187 "chip->intpin_reg_wpermit_reg2=%x, " in pch_phub_save_reg_conf()
188 "chip->intpin_reg_wpermit_reg3=%x\n", __func__, in pch_phub_save_reg_conf()
189 chip->phub_id_reg, in pch_phub_save_reg_conf()
190 chip->q_pri_val_reg, in pch_phub_save_reg_conf()
191 chip->rc_q_maxsize_reg, in pch_phub_save_reg_conf()
192 chip->bri_q_maxsize_reg, in pch_phub_save_reg_conf()
193 chip->comp_resp_timeout_reg, in pch_phub_save_reg_conf()
194 chip->bus_slave_control_reg, in pch_phub_save_reg_conf()
195 chip->deadlock_avoid_type_reg, in pch_phub_save_reg_conf()
196 chip->intpin_reg_wpermit_reg0, in pch_phub_save_reg_conf()
197 chip->intpin_reg_wpermit_reg1, in pch_phub_save_reg_conf()
198 chip->intpin_reg_wpermit_reg2, in pch_phub_save_reg_conf()
199 chip->intpin_reg_wpermit_reg3); in pch_phub_save_reg_conf()
201 chip->int_reduce_control_reg[i] = in pch_phub_save_reg_conf()
203 dev_dbg(&pdev->dev, "%s : " in pch_phub_save_reg_conf()
204 "chip->int_reduce_control_reg[%d]=%x\n", in pch_phub_save_reg_conf()
205 __func__, i, chip->int_reduce_control_reg[i]); in pch_phub_save_reg_conf()
207 chip->clkcfg_reg = ioread32(p + CLKCFG_REG_OFFSET); in pch_phub_save_reg_conf()
208 if ((chip->ioh_type == 2) || (chip->ioh_type == 4)) in pch_phub_save_reg_conf()
209 chip->funcsel_reg = ioread32(p + FUNCSEL_REG_OFFSET); in pch_phub_save_reg_conf()
212 /* pch_phub_restore_reg_conf - restore register configuration */
218 p = chip->pch_phub_base_address; in pch_phub_restore_reg_conf()
220 iowrite32(chip->phub_id_reg, p + PCH_PHUB_ID_REG); in pch_phub_restore_reg_conf()
221 iowrite32(chip->q_pri_val_reg, p + PCH_PHUB_QUEUE_PRI_VAL_REG); in pch_phub_restore_reg_conf()
222 iowrite32(chip->rc_q_maxsize_reg, p + PCH_PHUB_RC_QUEUE_MAXSIZE_REG); in pch_phub_restore_reg_conf()
223 iowrite32(chip->bri_q_maxsize_reg, p + PCH_PHUB_BRI_QUEUE_MAXSIZE_REG); in pch_phub_restore_reg_conf()
224 iowrite32(chip->comp_resp_timeout_reg, in pch_phub_restore_reg_conf()
226 iowrite32(chip->bus_slave_control_reg, in pch_phub_restore_reg_conf()
228 iowrite32(chip->deadlock_avoid_type_reg, in pch_phub_restore_reg_conf()
230 iowrite32(chip->intpin_reg_wpermit_reg0, in pch_phub_restore_reg_conf()
232 iowrite32(chip->intpin_reg_wpermit_reg1, in pch_phub_restore_reg_conf()
234 iowrite32(chip->intpin_reg_wpermit_reg2, in pch_phub_restore_reg_conf()
236 iowrite32(chip->intpin_reg_wpermit_reg3, in pch_phub_restore_reg_conf()
238 dev_dbg(&pdev->dev, "%s : " in pch_phub_restore_reg_conf()
239 "chip->phub_id_reg=%x, " in pch_phub_restore_reg_conf()
240 "chip->q_pri_val_reg=%x, " in pch_phub_restore_reg_conf()
241 "chip->rc_q_maxsize_reg=%x, " in pch_phub_restore_reg_conf()
242 "chip->bri_q_maxsize_reg=%x, " in pch_phub_restore_reg_conf()
243 "chip->comp_resp_timeout_reg=%x, " in pch_phub_restore_reg_conf()
244 "chip->bus_slave_control_reg=%x, " in pch_phub_restore_reg_conf()
245 "chip->deadlock_avoid_type_reg=%x, " in pch_phub_restore_reg_conf()
246 "chip->intpin_reg_wpermit_reg0=%x, " in pch_phub_restore_reg_conf()
247 "chip->intpin_reg_wpermit_reg1=%x, " in pch_phub_restore_reg_conf()
248 "chip->intpin_reg_wpermit_reg2=%x, " in pch_phub_restore_reg_conf()
249 "chip->intpin_reg_wpermit_reg3=%x\n", __func__, in pch_phub_restore_reg_conf()
250 chip->phub_id_reg, in pch_phub_restore_reg_conf()
251 chip->q_pri_val_reg, in pch_phub_restore_reg_conf()
252 chip->rc_q_maxsize_reg, in pch_phub_restore_reg_conf()
253 chip->bri_q_maxsize_reg, in pch_phub_restore_reg_conf()
254 chip->comp_resp_timeout_reg, in pch_phub_restore_reg_conf()
255 chip->bus_slave_control_reg, in pch_phub_restore_reg_conf()
256 chip->deadlock_avoid_type_reg, in pch_phub_restore_reg_conf()
257 chip->intpin_reg_wpermit_reg0, in pch_phub_restore_reg_conf()
258 chip->intpin_reg_wpermit_reg1, in pch_phub_restore_reg_conf()
259 chip->intpin_reg_wpermit_reg2, in pch_phub_restore_reg_conf()
260 chip->intpin_reg_wpermit_reg3); in pch_phub_restore_reg_conf()
262 iowrite32(chip->int_reduce_control_reg[i], in pch_phub_restore_reg_conf()
264 dev_dbg(&pdev->dev, "%s : " in pch_phub_restore_reg_conf()
265 "chip->int_reduce_control_reg[%d]=%x\n", in pch_phub_restore_reg_conf()
266 __func__, i, chip->int_reduce_control_reg[i]); in pch_phub_restore_reg_conf()
269 iowrite32(chip->clkcfg_reg, p + CLKCFG_REG_OFFSET); in pch_phub_restore_reg_conf()
270 if ((chip->ioh_type == 2) || (chip->ioh_type == 4)) in pch_phub_restore_reg_conf()
271 iowrite32(chip->funcsel_reg, p + FUNCSEL_REG_OFFSET); in pch_phub_restore_reg_conf()
275 * pch_phub_read_serial_rom() - Reading Serial ROM
277 * @offset_address: Serial ROM offset address to read.
283 void __iomem *mem_addr = chip->pch_phub_extrom_base_address + in pch_phub_read_serial_rom()
290 * pch_phub_write_serial_rom() - Writing Serial ROM
292 * @offset_address: Serial ROM offset address.
298 void __iomem *mem_addr = chip->pch_phub_extrom_base_address + in pch_phub_write_serial_rom()
308 chip->pch_phub_extrom_base_address + PHUB_CONTROL); in pch_phub_write_serial_rom()
314 while (ioread8(chip->pch_phub_extrom_base_address + in pch_phub_write_serial_rom()
318 return -ETIMEDOUT; in pch_phub_write_serial_rom()
323 chip->pch_phub_extrom_base_address + PHUB_CONTROL); in pch_phub_write_serial_rom()
329 * pch_phub_read_serial_rom_val() - Read Serial ROM value
331 * @offset_address: Serial ROM address offset value.
339 mem_addr = chip->pch_mac_start_address + in pch_phub_read_serial_rom_val()
346 * pch_phub_write_serial_rom_val() - writing Serial ROM value
348 * @offset_address: Serial ROM address offset value.
357 mem_addr = chip->pch_mac_start_address + in pch_phub_write_serial_rom_val()
365 /* pch_phub_gbe_serial_rom_conf - makes Serial ROM header format configuration
366 * for Gigabit Ethernet MAC address
405 /* pch_phub_gbe_serial_rom_conf_mp - makes SerialROM header format configuration
406 * for Gigabit Ethernet MAC address
448 * pch_phub_read_gbe_mac_addr() - Read Gigabit Ethernet MAC address
450 * @data: Buffer of the Gigabit Ethernet MAC address value.
460 * pch_phub_write_gbe_mac_addr() - Write MAC address
462 * @data: Gigabit Ethernet MAC address value.
469 if ((chip->ioh_type == 1) || (chip->ioh_type == 5)) /* EG20T or ML7831*/ in pch_phub_write_gbe_mac_addr()
502 err = -ERESTARTSYS; in pch_phub_bin_read()
507 chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size); in pch_phub_bin_read()
508 if (!chip->pch_phub_extrom_base_address) { in pch_phub_bin_read()
509 err = -ENODATA; in pch_phub_bin_read()
513 pch_phub_read_serial_rom(chip, chip->pch_opt_rom_start_address, in pch_phub_bin_read()
516 pch_phub_read_serial_rom(chip, chip->pch_opt_rom_start_address + 1, in pch_phub_bin_read()
521 chip->pch_opt_rom_start_address + 2, in pch_phub_bin_read()
535 chip->pch_opt_rom_start_address + addr_offset + off, in pch_phub_bin_read()
539 err = -ENODATA; in pch_phub_bin_read()
543 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address); in pch_phub_bin_read()
548 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address); in pch_phub_bin_read()
567 return -ERESTARTSYS; in pch_phub_bin_write()
578 chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size); in pch_phub_bin_write()
579 if (!chip->pch_phub_extrom_base_address) { in pch_phub_bin_write()
580 err = -ENOMEM; in pch_phub_bin_write()
589 chip->pch_opt_rom_start_address + addr_offset + off, in pch_phub_bin_write()
598 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address); in pch_phub_bin_write()
603 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address); in pch_phub_bin_write()
613 u8 mac[8]; in show_pch_mac() local
617 chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size); in show_pch_mac()
618 if (!chip->pch_phub_extrom_base_address) in show_pch_mac()
619 return -ENOMEM; in show_pch_mac()
621 pch_phub_read_gbe_mac_addr(chip, mac); in show_pch_mac()
622 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address); in show_pch_mac()
624 return sprintf(buf, "%pM\n", mac); in show_pch_mac()
630 u8 mac[ETH_ALEN]; in store_pch_mac() local
635 if (!mac_pton(buf, mac)) in store_pch_mac()
636 return -EINVAL; in store_pch_mac()
638 chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size); in store_pch_mac()
639 if (!chip->pch_phub_extrom_base_address) in store_pch_mac()
640 return -ENOMEM; in store_pch_mac()
642 ret = pch_phub_write_gbe_mac_addr(chip, mac); in store_pch_mac()
643 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address); in store_pch_mac()
670 return -ENOMEM; in pch_phub_probe()
674 dev_err(&pdev->dev, in pch_phub_probe()
678 dev_dbg(&pdev->dev, "%s : pci_enable_device returns %d\n", __func__, in pch_phub_probe()
683 dev_err(&pdev->dev, in pch_phub_probe()
687 dev_dbg(&pdev->dev, "%s : " in pch_phub_probe()
690 chip->pch_phub_base_address = pci_iomap(pdev, 1, 0); in pch_phub_probe()
693 if (chip->pch_phub_base_address == NULL) { in pch_phub_probe()
694 dev_err(&pdev->dev, "%s : pci_iomap FAILED", __func__); in pch_phub_probe()
695 ret = -ENOMEM; in pch_phub_probe()
698 dev_dbg(&pdev->dev, "%s : pci_iomap SUCCESS and value " in pch_phub_probe()
700 chip->pch_phub_base_address); in pch_phub_probe()
702 chip->pdev = pdev; /* Save pci device struct */ in pch_phub_probe()
704 if (id->driver_data == 1) { /* EG20T PCH */ in pch_phub_probe()
708 if (pdev->dev.of_node) in pch_phub_probe()
709 of_property_read_u32(pdev->dev.of_node, in pch_phub_probe()
710 "intel,eg20t-prefetch", in pch_phub_probe()
713 ret = sysfs_create_file(&pdev->dev.kobj, in pch_phub_probe()
718 ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr); in pch_phub_probe()
727 /* quirk for CM-iTC board */ in pch_phub_probe()
729 if (board_name && strstr(board_name, "CM-iTC")) in pch_phub_probe()
737 iowrite32(prefetch, chip->pch_phub_base_address + 0x14); in pch_phub_probe()
739 iowrite32(0x25, chip->pch_phub_base_address + 0x44); in pch_phub_probe()
740 chip->pch_opt_rom_start_address = PCH_PHUB_ROM_START_ADDR_EG20T; in pch_phub_probe()
741 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_EG20T; in pch_phub_probe()
744 if (pdev->dev.of_node) { in pch_phub_probe()
752 } else if (id->driver_data == 2) { /* ML7213 IOH */ in pch_phub_probe()
753 ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr); in pch_phub_probe()
762 iowrite32(0x000affa0, chip->pch_phub_base_address + 0x14); in pch_phub_probe()
763 chip->pch_opt_rom_start_address =\ in pch_phub_probe()
765 } else if (id->driver_data == 3) { /* ML7223 IOH Bus-m*/ in pch_phub_probe()
769 iowrite32(0x000a0000, chip->pch_phub_base_address + 0x14); in pch_phub_probe()
771 iowrite32(0x25, chip->pch_phub_base_address + 0x140); in pch_phub_probe()
772 chip->pch_opt_rom_start_address =\ in pch_phub_probe()
774 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_ML7223; in pch_phub_probe()
775 } else if (id->driver_data == 4) { /* ML7223 IOH Bus-n*/ in pch_phub_probe()
776 ret = sysfs_create_file(&pdev->dev.kobj, in pch_phub_probe()
780 ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr); in pch_phub_probe()
788 iowrite32(0x0000ffa0, chip->pch_phub_base_address + 0x14); in pch_phub_probe()
789 chip->pch_opt_rom_start_address =\ in pch_phub_probe()
791 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_ML7223; in pch_phub_probe()
792 } else if (id->driver_data == 5) { /* ML7831 */ in pch_phub_probe()
793 ret = sysfs_create_file(&pdev->dev.kobj, in pch_phub_probe()
798 ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr); in pch_phub_probe()
803 iowrite32(0x000affaa, chip->pch_phub_base_address + 0x14); in pch_phub_probe()
805 iowrite32(0x25, chip->pch_phub_base_address + 0x44); in pch_phub_probe()
806 chip->pch_opt_rom_start_address = PCH_PHUB_ROM_START_ADDR_EG20T; in pch_phub_probe()
807 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_EG20T; in pch_phub_probe()
810 chip->ioh_type = id->driver_data; in pch_phub_probe()
815 sysfs_remove_file(&pdev->dev.kobj, &dev_attr_pch_mac.attr); in pch_phub_probe()
818 pci_iounmap(pdev, chip->pch_phub_base_address); in pch_phub_probe()
825 dev_err(&pdev->dev, "%s returns %d\n", __func__, ret); in pch_phub_probe()
833 sysfs_remove_file(&pdev->dev.kobj, &dev_attr_pch_mac.attr); in pch_phub_remove()
834 sysfs_remove_bin_file(&pdev->dev.kobj, &pch_bin_attr); in pch_phub_remove()
835 pci_iounmap(pdev, chip->pch_phub_base_address); in pch_phub_remove()