Lines Matching full:dpi
2 /* Marvell Octeon CN10K DPI driver
93 /* Message fields in word_l of DPI mailbox structure */
100 /* Message fields in word_h of DPI mailbox structure */
164 /* DPI device mailbox */
188 static inline void dpi_reg_write(struct dpipf *dpi, u64 offset, u64 val) in dpi_reg_write() argument
190 writeq(val, dpi->reg_base + offset); in dpi_reg_write()
193 static inline u64 dpi_reg_read(struct dpipf *dpi, u64 offset) in dpi_reg_read() argument
195 return readq(dpi->reg_base + offset); in dpi_reg_read()
198 static void dpi_wqe_cs_offset(struct dpipf *dpi, u8 offset) in dpi_wqe_cs_offset() argument
202 reg = dpi_reg_read(dpi, DPI_DMA_CONTROL); in dpi_wqe_cs_offset()
206 dpi_reg_write(dpi, DPI_DMA_CONTROL, reg); in dpi_wqe_cs_offset()
209 static int dpi_queue_init(struct dpipf *dpi, struct dpipf_vf *dpivf, u8 vf) in dpi_queue_init() argument
218 dpi_reg_write(dpi, DPI_DMAX_QRST(vf), DPI_DMA_QRST); in dpi_queue_init()
223 reg = dpi_reg_read(dpi, DPI_DMAX_QRST(vf)); in dpi_queue_init()
232 dev_err(&dpi->pdev->dev, "Queue reset failed\n"); in dpi_queue_init()
236 dpi_reg_write(dpi, DPI_DMAX_IDS2(vf), 0); in dpi_queue_init()
237 dpi_reg_write(dpi, DPI_DMAX_IDS(vf), 0); in dpi_queue_init()
240 dpi_reg_write(dpi, DPI_DMAX_IBUFF_CSIZE(vf), reg); in dpi_queue_init()
242 reg = dpi_reg_read(dpi, DPI_DMAX_IDS2(vf)); in dpi_queue_init()
244 dpi_reg_write(dpi, DPI_DMAX_IDS2(vf), reg); in dpi_queue_init()
246 reg = dpi_reg_read(dpi, DPI_DMAX_IDS(vf)); in dpi_queue_init()
251 dpi_reg_write(dpi, DPI_DMAX_IDS(vf), reg); in dpi_queue_init()
256 static void dpi_queue_fini(struct dpipf *dpi, u8 vf) in dpi_queue_fini() argument
258 dpi_reg_write(dpi, DPI_DMAX_QRST(vf), DPI_DMA_QRST); in dpi_queue_fini()
261 dpi_reg_write(dpi, DPI_DMAX_IDS2(vf), 0); in dpi_queue_fini()
262 dpi_reg_write(dpi, DPI_DMAX_IDS(vf), 0); in dpi_queue_fini()
267 struct dpipf *dpi = data; in dpi_mbox_intr_handler() local
271 reg = dpi_reg_read(dpi, DPI_MBOX_VF_PF_INT); in dpi_mbox_intr_handler()
273 for (vf = 0; vf < pci_num_vf(dpi->pdev); vf++) { in dpi_mbox_intr_handler()
275 schedule_work(&dpi->mbox[vf]->work); in dpi_mbox_intr_handler()
277 dpi_reg_write(dpi, DPI_MBOX_VF_PF_INT, reg); in dpi_mbox_intr_handler()
283 static int queue_config(struct dpipf *dpi, struct dpipf_vf *dpivf, struct dpi_mbox_message *msg) in queue_config() argument
296 ret = dpi_queue_init(dpi, dpivf, DPI_MBOX_VFID(msg->word_l)); in queue_config()
299 dpi_wqe_cs_offset(dpi, DPI_MBOX_WQES_OFFSET(msg->word_h)); in queue_config()
305 dpi_queue_fini(dpi, DPI_MBOX_VFID(msg->word_l)); in queue_config()
320 struct dpipf *dpi; in dpi_pfvf_mbox_work() local
323 dpi = mbox->pf; in dpi_pfvf_mbox_work()
332 if (vfid >= pci_num_vf(dpi->pdev)) in dpi_pfvf_mbox_work()
335 dpivf = &dpi->vf[vfid]; in dpi_pfvf_mbox_work()
338 ret = queue_config(dpi, dpivf, &msg); in dpi_pfvf_mbox_work()
348 static void dpi_setup_mbox_regs(struct dpipf *dpi, int vf) in dpi_setup_mbox_regs() argument
350 struct dpi_mbox *mbox = dpi->mbox[vf]; in dpi_setup_mbox_regs()
352 mbox->pf_vf_data_reg = dpi->reg_base + DPI_MBOX_PF_VF_DATA0(vf); in dpi_setup_mbox_regs()
353 mbox->vf_pf_data_reg = dpi->reg_base + DPI_MBOX_PF_VF_DATA1(vf); in dpi_setup_mbox_regs()
356 static int dpi_pfvf_mbox_setup(struct dpipf *dpi) in dpi_pfvf_mbox_setup() argument
361 dpi->mbox[vf] = devm_kzalloc(&dpi->pdev->dev, sizeof(*dpi->mbox[vf]), GFP_KERNEL); in dpi_pfvf_mbox_setup()
363 if (!dpi->mbox[vf]) in dpi_pfvf_mbox_setup()
366 mutex_init(&dpi->mbox[vf]->lock); in dpi_pfvf_mbox_setup()
367 INIT_WORK(&dpi->mbox[vf]->work, dpi_pfvf_mbox_work); in dpi_pfvf_mbox_setup()
368 dpi->mbox[vf]->pf = dpi; in dpi_pfvf_mbox_setup()
369 dpi_setup_mbox_regs(dpi, vf); in dpi_pfvf_mbox_setup()
375 static void dpi_pfvf_mbox_destroy(struct dpipf *dpi) in dpi_pfvf_mbox_destroy() argument
380 if (work_pending(&dpi->mbox[vf]->work)) in dpi_pfvf_mbox_destroy()
381 cancel_work_sync(&dpi->mbox[vf]->work); in dpi_pfvf_mbox_destroy()
383 dpi->mbox[vf] = NULL; in dpi_pfvf_mbox_destroy()
387 static void dpi_init(struct dpipf *dpi) in dpi_init() argument
399 dpi_reg_write(dpi, DPI_ENGX_BUF(engine), reg); in dpi_init()
405 dpi_reg_write(dpi, DPI_DMA_CONTROL, reg); in dpi_init()
406 dpi_reg_write(dpi, DPI_CTL, DPI_CTL_EN); in dpi_init()
412 reg = dpi_reg_read(dpi, DPI_EBUS_PORTX_CFG(port)); in dpi_init()
415 dpi_reg_write(dpi, DPI_EBUS_PORTX_CFG(port), reg); in dpi_init()
418 dpi_reg_write(dpi, DPI_WCTL_FIF_THR, DPI_WCTL_FIFO_THRESHOLD); in dpi_init()
421 static void dpi_fini(struct dpipf *dpi) in dpi_fini() argument
426 dpi_reg_write(dpi, DPI_ENGX_BUF(engine), 0); in dpi_fini()
428 dpi_reg_write(dpi, DPI_DMA_CONTROL, 0); in dpi_fini()
429 dpi_reg_write(dpi, DPI_CTL, 0); in dpi_fini()
437 static int dpi_irq_init(struct dpipf *dpi) in dpi_irq_init() argument
439 struct pci_dev *pdev = dpi->pdev; in dpi_irq_init()
444 dpi_reg_write(dpi, DPI_PF_RAS, DPI_PF_RAS_INT); in dpi_irq_init()
447 dpi_reg_write(dpi, DPI_PF_RAS_ENA_W1C, DPI_PF_RAS_INT); in dpi_irq_init()
450 dpi_reg_write(dpi, DPI_REQQX_INT(i), DPI_REQQ_INT); in dpi_irq_init()
451 dpi_reg_write(dpi, DPI_REQQX_INT_ENA_W1C(i), DPI_REQQ_INT); in dpi_irq_init()
455 dpi_reg_write(dpi, DPI_DMA_CCX_INT(i), DPI_DMA_CC_INT); in dpi_irq_init()
456 dpi_reg_write(dpi, DPI_DMA_CCX_INT_ENA_W1C(i), DPI_DMA_CC_INT); in dpi_irq_init()
461 dev_err(dev, "DPI: Failed to alloc %d msix irqs\n", DPI_MAX_IRQS); in dpi_irq_init()
467 dev_err(dev, "DPI: Failed to add irq free action\n"); in dpi_irq_init()
472 dpi_mbox_intr_handler, 0, "dpi-mbox", dpi); in dpi_irq_init()
474 dev_err(dev, "DPI: request_irq failed for mbox; err=%d\n", ret); in dpi_irq_init()
478 dpi_reg_write(dpi, DPI_MBOX_VF_PF_INT_ENA_W1S, GENMASK_ULL(31, 0)); in dpi_irq_init()
483 static int dpi_mps_mrrs_config(struct dpipf *dpi, void __user *arg) in dpi_mps_mrrs_config() argument
510 reg = dpi_reg_read(dpi, DPI_EBUS_PORTX_CFG(cfg.port)); in dpi_mps_mrrs_config()
513 dpi_reg_write(dpi, DPI_EBUS_PORTX_CFG(cfg.port), reg); in dpi_mps_mrrs_config()
518 static int dpi_engine_config(struct dpipf *dpi, void __user *arg) in dpi_engine_config() argument
537 dpi_reg_write(dpi, DPI_ENGX_BUF(engine), eng_buf[engine]); in dpi_engine_config()
543 dpi_reg_write(dpi, DPI_DMA_ENGX_EN(engine), reg); in dpi_engine_config()
557 struct dpipf *dpi; in dpi_dev_ioctl() local
560 dpi = container_of(fptr->private_data, struct dpipf, miscdev); in dpi_dev_ioctl()
564 ret = dpi_mps_mrrs_config(dpi, arg); in dpi_dev_ioctl()
567 ret = dpi_engine_config(dpi, arg); in dpi_dev_ioctl()
586 struct dpipf *dpi; in dpi_probe() local
589 dpi = devm_kzalloc(dev, sizeof(*dpi), GFP_KERNEL); in dpi_probe()
590 if (!dpi) in dpi_probe()
593 dpi->pdev = pdev; in dpi_probe()
597 dev_err(dev, "DPI: Failed to enable PCI device\n"); in dpi_probe()
603 dev_err(dev, "DPI: Failed to request MMIO region\n"); in dpi_probe()
607 dpi->reg_base = pcim_iomap_table(pdev)[PCI_DPI_CFG_BAR]; in dpi_probe()
610 dpi_init(dpi); in dpi_probe()
613 ret = dpi_pfvf_mbox_setup(dpi); in dpi_probe()
615 dev_err(dev, "DPI: Failed to setup pf-vf mbox\n"); in dpi_probe()
620 ret = dpi_irq_init(dpi); in dpi_probe()
622 dev_err(dev, "DPI: Failed to initialize irq vectors\n"); in dpi_probe()
626 pci_set_drvdata(pdev, dpi); in dpi_probe()
627 dpi->miscdev.minor = MISC_DYNAMIC_MINOR; in dpi_probe()
628 dpi->miscdev.name = KBUILD_MODNAME; in dpi_probe()
629 dpi->miscdev.fops = &dpi_device_fops; in dpi_probe()
630 dpi->miscdev.parent = dev; in dpi_probe()
632 ret = misc_register(&dpi->miscdev); in dpi_probe()
634 dev_err(dev, "DPI: Failed to register misc device\n"); in dpi_probe()
641 dpi_pfvf_mbox_destroy(dpi); in dpi_probe()
643 dpi_fini(dpi); in dpi_probe()
649 struct dpipf *dpi = pci_get_drvdata(pdev); in dpi_remove() local
651 misc_deregister(&dpi->miscdev); in dpi_remove()
653 dpi_pfvf_mbox_destroy(dpi); in dpi_remove()
654 dpi_fini(dpi); in dpi_remove()
675 MODULE_DESCRIPTION("Marvell Octeon CN10K DPI Driver");