Lines Matching +full:0 +full:x1040

30 #define PCI_CFG_TXE_FW_STS0   0x40
31 #  define PCI_CFG_TXE_FW_STS0_WRK_ST_MSK    0x0000000F
32 #  define PCI_CFG_TXE_FW_STS0_OP_ST_MSK     0x000001C0
33 #  define PCI_CFG_TXE_FW_STS0_FW_INIT_CMPLT 0x00000200
34 #  define PCI_CFG_TXE_FW_STS0_ERR_CODE_MSK  0x0000F000
35 #  define PCI_CFG_TXE_FW_STS0_OP_MODE_MSK   0x000F0000
36 #  define PCI_CFG_TXE_FW_STS0_RST_CNT_MSK   0x00F00000
37 #define PCI_CFG_TXE_FW_STS1   0x48
39 #define IPC_BASE_ADDR	0x80400 /* SeC IPC Base Address */
42 #define SEC_IPC_INPUT_DOORBELL_REG       (0x0000 + IPC_BASE_ADDR)
50 #define SEC_IPC_INPUT_STATUS_REG         (0x0008 + IPC_BASE_ADDR)
51 #  define SEC_IPC_INPUT_STATUS_RDY    BIT(0)
54 #define SEC_IPC_HOST_INT_STATUS_REG      (0x0010 + IPC_BASE_ADDR)
55 #define   SEC_IPC_HOST_INT_STATUS_OUT_DB             BIT(0)
69 #define SEC_IPC_HOST_INT_MASK_REG        (0x0014 + IPC_BASE_ADDR)
71 #  define SEC_IPC_HOST_INT_MASK_OUT_DB	BIT(0) /* Output Doorbell Int Mask */
75 #define SEC_IPC_INPUT_PAYLOAD_REG        (0x0100 + IPC_BASE_ADDR)
77 #define IPC_SHARED_PAYLOAD_REG           (0x0200 + IPC_BASE_ADDR)
83 #define SATT2_CTRL_REG                   0x1040
84 #  define SATT2_CTRL_VALID_MSK            BIT(0)
89 #define SATT2_SAP_BA_REG                 0x1044
91 #define SATT2_SAP_SIZE_REG               0x1048
93 #define SATT2_BRG_BA_LSB_REG             0x104C
96 #define HHISR_REG                        0x2020
104 #define HHIER_REG                        0x2024
105 #define   IPC_HHIER_SEC	BIT(0)
114 #define HHIMR_REG                        0x2028
115 #define   IPC_HHIMR_SEC       BIT(0)
119 #define HHIRQSR_REG                      0x202C
121 /* Host Interrupt Cause Register 0 - SeC IPC Readiness
128 #define HICR_SEC_IPC_READINESS_REG       0x2040
129 #define   HICR_SEC_IPC_READINESS_HOST_RDY  BIT(0)
141 #define HICR_HOST_ALIVENESS_RESP_REG     0x2044
142 #define   HICR_HOST_ALIVENESS_RESP_ACK    BIT(0)
145 #define HICR_SEC_IPC_OUTPUT_DOORBELL_REG 0x2048
160 #define HISR_REG                         0x2060
161 #define   HISR_INT_0_STS      BIT(0)
173 #define HIER_REG                         0x2064
174 #define   HIER_INT_0_EN      BIT(0)
191 #define BRIDGE_IPC_OUTPUT_PAYLOAD_REG    0x20C0
198 #define SICR_HOST_ALIVENESS_REQ_REG      0x214C
199 #define   SICR_HOST_ALIVENESS_REQ_REQUESTED    BIT(0)
209 #define SICR_HOST_IPC_READINESS_REQ_REG  0x2150
212 #define SICR_HOST_IPC_READINESS_HOST_RDY  BIT(0)
226 #define SICR_SEC_IPC_OUTPUT_STATUS_REG   0x2154
227 #  define SEC_IPC_OUTPUT_STATUS_RDY BIT(0)