141 	u32 hcsr;  in mei_hcsr_set_hig()  local
143 	hcsr = mei_hcsr_read(dev) | H_IG;  in mei_hcsr_set_hig()
144 	mei_hcsr_set(dev, hcsr);  in mei_hcsr_set_hig()
243 	u32 hcsr, reg;  in mei_me_hw_config()  local
249 	hcsr = mei_hcsr_read(dev);  in mei_me_hw_config()
250 	hw->hbuf_depth = (hcsr & H_CBD) >> 24;  in mei_me_hw_config()
283 static inline u32 me_intr_src(u32 hcsr)  in me_intr_src()  argument
285 	return hcsr & H_CSR_IS_MASK;  in me_intr_src()
295 static inline void me_intr_disable(struct mei_device *dev, u32 hcsr)  in me_intr_disable()  argument
297 	hcsr &= ~H_CSR_IE_MASK;  in me_intr_disable()
298 	mei_hcsr_set(dev, hcsr);  in me_intr_disable()
307 static inline void me_intr_clear(struct mei_device *dev, u32 hcsr)  in me_intr_clear()  argument
309 	if (me_intr_src(hcsr))  in me_intr_clear()
310 		mei_hcsr_write(dev, hcsr);  in me_intr_clear()
320 	u32 hcsr = mei_hcsr_read(dev);  in mei_me_intr_clear()  local
322 	me_intr_clear(dev, hcsr);  in mei_me_intr_clear()
331 	u32 hcsr;  in mei_me_intr_enable()  local
336 	hcsr = mei_hcsr_read(dev) | H_CSR_IE_MASK;  in mei_me_intr_enable()
337 	mei_hcsr_set(dev, hcsr);  in mei_me_intr_enable()
347 	u32 hcsr = mei_hcsr_read(dev);  in mei_me_intr_disable()  local
349 	me_intr_disable(dev, hcsr);  in mei_me_intr_disable()
374 	u32 hcsr = mei_hcsr_read(dev);  in mei_me_hw_reset_release()  local
376 	hcsr |= H_IG;  in mei_me_hw_reset_release()
377 	hcsr &= ~H_RST;  in mei_me_hw_reset_release()
378 	mei_hcsr_set(dev, hcsr);  in mei_me_hw_reset_release()
388 	u32 hcsr = mei_hcsr_read(dev);  in mei_me_host_set_ready()  local
391 		hcsr |= H_CSR_IE_MASK;  in mei_me_host_set_ready()
393 	hcsr |=  H_IG | H_RDY;  in mei_me_host_set_ready()
394 	mei_hcsr_set(dev, hcsr);  in mei_me_host_set_ready()
405 	u32 hcsr = mei_hcsr_read(dev);  in mei_me_host_is_ready()  local
407 	return (hcsr & H_RDY) == H_RDY;  in mei_me_host_is_ready()
563 	u32 hcsr;  in mei_hbuf_filled_slots()  local
566 	hcsr = mei_hcsr_read(dev);  in mei_hbuf_filled_slots()
568 	read_ptr = (char) ((hcsr & H_CBRP) >> 8);  in mei_hbuf_filled_slots()
569 	write_ptr = (char) ((hcsr & H_CBWP) >> 16);  in mei_hbuf_filled_slots()
1240 	u32 hcsr;  in mei_me_hw_reset()  local
1255 	hcsr = mei_hcsr_read(dev);  in mei_me_hw_reset()
1261 	if ((hcsr & H_RST) == H_RST) {  in mei_me_hw_reset()
1262 		dev_warn(dev->dev, "H_RST is set = 0x%08X", hcsr);  in mei_me_hw_reset()
1263 		hcsr &= ~H_RST;  in mei_me_hw_reset()
1264 		mei_hcsr_set(dev, hcsr);  in mei_me_hw_reset()
1265 		hcsr = mei_hcsr_read(dev);  in mei_me_hw_reset()
1268 	hcsr |= H_RST | H_IG | H_CSR_IS_MASK;  in mei_me_hw_reset()
1271 		hcsr &= ~H_CSR_IE_MASK;  in mei_me_hw_reset()
1274 	mei_hcsr_write(dev, hcsr);  in mei_me_hw_reset()
1280 	hcsr = mei_hcsr_read(dev);  in mei_me_hw_reset()
1282 	if ((hcsr & H_RST) == 0)  in mei_me_hw_reset()
1283 		dev_warn(dev->dev, "H_RST is not set = 0x%08X", hcsr);  in mei_me_hw_reset()
1285 	if ((hcsr & H_RDY) == H_RDY)  in mei_me_hw_reset()
1286 		dev_warn(dev->dev, "H_RDY is not cleared 0x%08X", hcsr);  in mei_me_hw_reset()
1310 	u32 hcsr;  in mei_me_irq_quick_handler()  local
1312 	hcsr = mei_hcsr_read(dev);  in mei_me_irq_quick_handler()
1313 	if (!me_intr_src(hcsr))  in mei_me_irq_quick_handler()
1316 	dev_dbg(dev->dev, "interrupt source 0x%08X\n", me_intr_src(hcsr));  in mei_me_irq_quick_handler()
1319 	me_intr_disable(dev, hcsr);  in mei_me_irq_quick_handler()
1339 	u32 hcsr;  in mei_me_irq_thread_handler()  local
1346 	hcsr = mei_hcsr_read(dev);  in mei_me_irq_thread_handler()
1347 	me_intr_clear(dev, hcsr);  in mei_me_irq_thread_handler()
1371 	mei_me_pg_intr(dev, me_intr_src(hcsr));  in mei_me_irq_thread_handler()
1459 		u32 hcsr;  in mei_me_polling_thread()  local
1468 		hcsr = mei_hcsr_read(dev);  in mei_me_polling_thread()
1469 		if (me_intr_src(hcsr)) {  in mei_me_polling_thread()