misc/mei/hw-me-regs.h

1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3  * Copyright (c) 2003-2022, Intel Corporation. All rights reserved.
45 #define MEI_DEV_ID_CPT_1      0x1C3A  /* Couger Point */
48 #define MEI_DEV_ID_PPT_1      0x1E3A  /* Panther Point */
49 #define MEI_DEV_ID_PPT_2      0x1CBA  /* Panther Point */
50 #define MEI_DEV_ID_PPT_3      0x1DBA  /* Panther Point */
52 #define MEI_DEV_ID_LPT_H      0x8C3A  /* Lynx Point H */
53 #define MEI_DEV_ID_LPT_W      0x8D3A  /* Lynx Point - Wellsburg */
54 #define MEI_DEV_ID_LPT_LP     0x9C3A  /* Lynx Point LP */
55 #define MEI_DEV_ID_LPT_HR     0x8CBA  /* Lynx Point H Refresh */
57 #define MEI_DEV_ID_WPT_LP     0x9CBA  /* Wildcat Point LP */
58 #define MEI_DEV_ID_WPT_LP_2   0x9CBB  /* Wildcat Point LP 2 */
60 #define MEI_DEV_ID_SPT        0x9D3A  /* Sunrise Point */
61 #define MEI_DEV_ID_SPT_2      0x9D3B  /* Sunrise Point 2 */
62 #define MEI_DEV_ID_SPT_3      0x9D3E  /* Sunrise Point 3 (iToutch) */
63 #define MEI_DEV_ID_SPT_H      0xA13A  /* Sunrise Point H */
64 #define MEI_DEV_ID_SPT_H_2    0xA13B  /* Sunrise Point H 2 */
75 #define MEI_DEV_ID_KBP        0xA2BA  /* Kaby Point */
76 #define MEI_DEV_ID_KBP_2      0xA2BB  /* Kaby Point 2 */
77 #define MEI_DEV_ID_KBP_3      0xA2BE  /* Kaby Point 3 (iTouch) */
79 #define MEI_DEV_ID_CNP_LP     0x9DE0  /* Cannon Point LP */
80 #define MEI_DEV_ID_CNP_LP_3   0x9DE4  /* Cannon Point LP 3 (iTouch) */
81 #define MEI_DEV_ID_CNP_H      0xA360  /* Cannon Point H */
82 #define MEI_DEV_ID_CNP_H_3    0xA364  /* Cannon Point H 3 (iTouch) */
84 #define MEI_DEV_ID_CMP_LP     0x02e0  /* Comet Point LP */
85 #define MEI_DEV_ID_CMP_LP_3   0x02e4  /* Comet Point LP 3 (iTouch) */
87 #define MEI_DEV_ID_CMP_V      0xA3BA  /* Comet Point Lake V */
94 #define MEI_DEV_ID_ICP_LP     0x34E0  /* Ice Lake Point LP */
95 #define MEI_DEV_ID_ICP_N      0x38E0  /* Ice Lake Point N */
97 #define MEI_DEV_ID_JSP_N      0x4DE0  /* Jasper Lake Point N */
99 #define MEI_DEV_ID_TGP_LP     0xA0E0  /* Tiger Lake Point LP */
100 #define MEI_DEV_ID_TGP_H      0x43E0  /* Tiger Lake Point H */
107 #define MEI_DEV_ID_ADP_S      0x7AE8  /* Alder Lake Point S */
108 #define MEI_DEV_ID_ADP_LP     0x7A60  /* Alder Lake Point LP */
109 #define MEI_DEV_ID_ADP_P      0x51E0  /* Alder Lake Point P */
110 #define MEI_DEV_ID_ADP_N      0x54E0  /* Alder Lake Point N */
112 #define MEI_DEV_ID_RPL_S      0x7A68  /* Raptor Lake Point S */
114 #define MEI_DEV_ID_MTL_M      0x7E70  /* Meteor Lake Point M */
115 #define MEI_DEV_ID_ARL_S      0x7F68  /* Arrow Lake Point S */
116 #define MEI_DEV_ID_ARL_H      0x7770  /* Arrow Lake Point H */
118 #define MEI_DEV_ID_LNL_M      0xA870  /* Lunar Lake Point M */
130 #  define PCI_CFG_HFS_2_PM_CMOFF_TO_CMX_ERROR 0x1000000 /* CMoff->CMx wake after an error */
144 /* H_CB_WW - Host Circular Buffer (CB) Write Window register */
146 /* H_CSR - Host Control Status register */
148 /* ME_CB_RW - ME Circular Buffer Read Window register (read only) */
150 /* ME_CSR_HA - ME Control Status Host Access register (read only) */
152 /* H_HGC_CSR - PGI register */
154 /* H_D0I3C - D0I3 Control  */
163 /* Host Circular Buffer Depth - maximum number of 32-bit entries in CB */
189 /* ME CB (Circular Buffer) Depth HRA (Host Read Access) - host read only
192 /* ME CB Write Pointer HRA - host read only access to ME_CBWP */
194 /* ME CB Read Pointer HRA - host read only access to ME_CBRP */
196 /* ME Power Gate Isolation Capability HRA  - host ready only access */
198 /* ME Reset HRA - host read only access to ME_RST */
200 /* ME Ready HRA - host read only access to ME_RDY */
202 /* ME Interrupt Generate HRA - host read only access to ME_IG */
204 /* ME Interrupt Status HRA - host read only access to ME_IS */
206 /* ME Interrupt Enable HRA - host read only access to ME_IE */