Lines Matching +full:0 +full:- +full:63
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
21 #include <misc/cxl-base.h>
64 /* Configuration and Control area - CAIA 1&2 */
65 static const cxl_p1_reg_t CXL_PSL_CtxTime = {0x0000};
66 static const cxl_p1_reg_t CXL_PSL_ErrIVTE = {0x0008};
67 static const cxl_p1_reg_t CXL_PSL_KEY1 = {0x0010};
68 static const cxl_p1_reg_t CXL_PSL_KEY2 = {0x0018};
69 static const cxl_p1_reg_t CXL_PSL_Control = {0x0020};
71 static const cxl_p1_reg_t CXL_PSL_DLCNTL = {0x0060};
72 static const cxl_p1_reg_t CXL_PSL_DLADDR = {0x0068};
74 /* PSL Lookaside Buffer Management Area - CAIA 1 */
75 static const cxl_p1_reg_t CXL_PSL_LBISEL = {0x0080};
76 static const cxl_p1_reg_t CXL_PSL_SLBIE = {0x0088};
77 static const cxl_p1_reg_t CXL_PSL_SLBIA = {0x0090};
78 static const cxl_p1_reg_t CXL_PSL_TLBIE = {0x00A0};
79 static const cxl_p1_reg_t CXL_PSL_TLBIA = {0x00A8};
80 static const cxl_p1_reg_t CXL_PSL_AFUSEL = {0x00B0};
82 /* 0x00C0:7EFF Implementation dependent area */
83 /* PSL registers - CAIA 1 */
84 static const cxl_p1_reg_t CXL_PSL_FIR1 = {0x0100};
85 static const cxl_p1_reg_t CXL_PSL_FIR2 = {0x0108};
86 static const cxl_p1_reg_t CXL_PSL_Timebase = {0x0110};
87 static const cxl_p1_reg_t CXL_PSL_VERSION = {0x0118};
88 static const cxl_p1_reg_t CXL_PSL_RESLCKTO = {0x0128};
89 static const cxl_p1_reg_t CXL_PSL_TB_CTLSTAT = {0x0140};
90 static const cxl_p1_reg_t CXL_PSL_FIR_CNTL = {0x0148};
91 static const cxl_p1_reg_t CXL_PSL_DSNDCTL = {0x0150};
92 static const cxl_p1_reg_t CXL_PSL_SNWRALLOC = {0x0158};
93 static const cxl_p1_reg_t CXL_PSL_TRACE = {0x0170};
94 /* PSL registers - CAIA 2 */
95 static const cxl_p1_reg_t CXL_PSL9_CONTROL = {0x0020};
96 static const cxl_p1_reg_t CXL_XSL9_INV = {0x0110};
97 static const cxl_p1_reg_t CXL_XSL9_DBG = {0x0130};
98 static const cxl_p1_reg_t CXL_XSL9_DEF = {0x0140};
99 static const cxl_p1_reg_t CXL_XSL9_DSNCTL = {0x0168};
100 static const cxl_p1_reg_t CXL_PSL9_FIR1 = {0x0300};
101 static const cxl_p1_reg_t CXL_PSL9_FIR_MASK = {0x0308};
102 static const cxl_p1_reg_t CXL_PSL9_Timebase = {0x0310};
103 static const cxl_p1_reg_t CXL_PSL9_DEBUG = {0x0320};
104 static const cxl_p1_reg_t CXL_PSL9_FIR_CNTL = {0x0348};
105 static const cxl_p1_reg_t CXL_PSL9_DSNDCTL = {0x0350};
106 static const cxl_p1_reg_t CXL_PSL9_TB_CTLSTAT = {0x0340};
107 static const cxl_p1_reg_t CXL_PSL9_TRACECFG = {0x0368};
108 static const cxl_p1_reg_t CXL_PSL9_APCDEDALLOC = {0x0378};
109 static const cxl_p1_reg_t CXL_PSL9_APCDEDTYPE = {0x0380};
110 static const cxl_p1_reg_t CXL_PSL9_TNR_ADDR = {0x0388};
111 static const cxl_p1_reg_t CXL_PSL9_CTCCFG = {0x0390};
112 static const cxl_p1_reg_t CXL_PSL9_GP_CT = {0x0398};
113 static const cxl_p1_reg_t CXL_XSL9_IERAT = {0x0588};
114 static const cxl_p1_reg_t CXL_XSL9_ILPP = {0x0590};
116 /* 0x7F00:7FFF Reserved PCIe MSI-X Pending Bit Array area */
117 /* 0x8000:FFFF Reserved PCIe MSI-X Table Area */
120 /* Configuration Area - CAIA 1&2 */
121 static const cxl_p1n_reg_t CXL_PSL_SR_An = {0x00};
122 static const cxl_p1n_reg_t CXL_PSL_LPID_An = {0x08};
123 static const cxl_p1n_reg_t CXL_PSL_AMBAR_An = {0x10};
124 static const cxl_p1n_reg_t CXL_PSL_SPOffset_An = {0x18};
125 static const cxl_p1n_reg_t CXL_PSL_ID_An = {0x20};
126 static const cxl_p1n_reg_t CXL_PSL_SERR_An = {0x28};
127 /* Memory Management and Lookaside Buffer Management - CAIA 1*/
128 static const cxl_p1n_reg_t CXL_PSL_SDR_An = {0x30};
129 /* Memory Management and Lookaside Buffer Management - CAIA 1&2 */
130 static const cxl_p1n_reg_t CXL_PSL_AMOR_An = {0x38};
131 /* Pointer Area - CAIA 1&2 */
132 static const cxl_p1n_reg_t CXL_HAURP_An = {0x80};
133 static const cxl_p1n_reg_t CXL_PSL_SPAP_An = {0x88};
134 static const cxl_p1n_reg_t CXL_PSL_LLCMD_An = {0x90};
135 /* Control Area - CAIA 1&2 */
136 static const cxl_p1n_reg_t CXL_PSL_SCNTL_An = {0xA0};
137 static const cxl_p1n_reg_t CXL_PSL_CtxTime_An = {0xA8};
138 static const cxl_p1n_reg_t CXL_PSL_IVTE_Offset_An = {0xB0};
139 static const cxl_p1n_reg_t CXL_PSL_IVTE_Limit_An = {0xB8};
140 /* 0xC0:FF Implementation Dependent Area - CAIA 1&2 */
141 static const cxl_p1n_reg_t CXL_PSL_FIR_SLICE_An = {0xC0};
142 static const cxl_p1n_reg_t CXL_AFU_DEBUG_An = {0xC8};
143 /* 0xC0:FF Implementation Dependent Area - CAIA 1 */
144 static const cxl_p1n_reg_t CXL_PSL_APCALLOC_A = {0xD0};
145 static const cxl_p1n_reg_t CXL_PSL_COALLOC_A = {0xD8};
146 static const cxl_p1n_reg_t CXL_PSL_RXCTL_A = {0xE0};
147 static const cxl_p1n_reg_t CXL_PSL_SLICE_TRACE = {0xE8};
150 /* Configuration and Control Area - CAIA 1&2 */
151 static const cxl_p2n_reg_t CXL_PSL_PID_TID_An = {0x000};
152 static const cxl_p2n_reg_t CXL_CSRP_An = {0x008};
153 /* Configuration and Control Area - CAIA 1 */
154 static const cxl_p2n_reg_t CXL_AURP0_An = {0x010};
155 static const cxl_p2n_reg_t CXL_AURP1_An = {0x018};
156 static const cxl_p2n_reg_t CXL_SSTP0_An = {0x020};
157 static const cxl_p2n_reg_t CXL_SSTP1_An = {0x028};
158 /* Configuration and Control Area - CAIA 1 */
159 static const cxl_p2n_reg_t CXL_PSL_AMR_An = {0x030};
160 /* Segment Lookaside Buffer Management - CAIA 1 */
161 static const cxl_p2n_reg_t CXL_SLBIE_An = {0x040};
162 static const cxl_p2n_reg_t CXL_SLBIA_An = {0x048};
163 static const cxl_p2n_reg_t CXL_SLBI_Select_An = {0x050};
164 /* Interrupt Registers - CAIA 1&2 */
165 static const cxl_p2n_reg_t CXL_PSL_DSISR_An = {0x060};
166 static const cxl_p2n_reg_t CXL_PSL_DAR_An = {0x068};
167 static const cxl_p2n_reg_t CXL_PSL_DSR_An = {0x070};
168 static const cxl_p2n_reg_t CXL_PSL_TFC_An = {0x078};
169 static const cxl_p2n_reg_t CXL_PSL_PEHandle_An = {0x080};
170 static const cxl_p2n_reg_t CXL_PSL_ErrStat_An = {0x088};
171 /* AFU Registers - CAIA 1&2 */
172 static const cxl_p2n_reg_t CXL_AFU_Cntl_An = {0x090};
173 static const cxl_p2n_reg_t CXL_AFU_ERR_An = {0x098};
174 /* Work Element Descriptor - CAIA 1&2 */
175 static const cxl_p2n_reg_t CXL_PSL_WED_An = {0x0A0};
176 /* 0x0C0:FFF Implementation Dependent Area */
178 #define CXL_PSL_SPAP_Addr 0x0ffffffffffff000ULL
179 #define CXL_PSL_SPAP_Size 0x0000000000000ff0ULL
181 #define CXL_PSL_SPAP_V 0x0000000000000001ULL
184 #define CXL_PSL_Control_tb (0x1ull << (63-63))
185 #define CXL_PSL_Control_Fr (0x1ull << (63-31))
186 #define CXL_PSL_Control_Fs_MASK (0x3ull << (63-29))
187 #define CXL_PSL_Control_Fs_Complete (0x3ull << (63-29))
190 #define CXL_PSL_DLCNTL_D (0x1ull << (63-28))
191 #define CXL_PSL_DLCNTL_C (0x1ull << (63-29))
192 #define CXL_PSL_DLCNTL_E (0x1ull << (63-30))
193 #define CXL_PSL_DLCNTL_S (0x1ull << (63-31))
199 #define CXL_PSL_SR_An_TA (1ull << (63-1)) /* Tags active, GA1: 0 */
200 #define CXL_PSL_SR_An_HV MSR_HV /* Hypervisor, GA1: 0 */
201 #define CXL_PSL_SR_An_XLAT_hpt (0ull << (63-6))/* Hashed page table (HPT) mode */
202 #define CXL_PSL_SR_An_XLAT_roh (2ull << (63-6))/* Radix on HPT mode */
203 #define CXL_PSL_SR_An_XLAT_ror (3ull << (63-6))/* Radix on Radix mode */
204 #define CXL_PSL_SR_An_BOT (1ull << (63-10)) /* Use the in-memory segment table */
206 #define CXL_PSL_SR_An_ISL (1ull << (63-53)) /* Ignore Segment Large Page */
207 #define CXL_PSL_SR_An_TC (1ull << (63-54)) /* Page Table secondary hash */
208 #define CXL_PSL_SR_An_US (1ull << (63-56)) /* User state, GA1: X */
209 #define CXL_PSL_SR_An_SC (1ull << (63-58)) /* Segment Table secondary hash */
211 #define CXL_PSL_SR_An_MP (1ull << (63-62)) /* Master Process */
212 #define CXL_PSL_SR_An_LE (1ull << (63-63)) /* Little Endian */
215 #define CXL_PSL_ID_An_F (1ull << (63-31))
216 #define CXL_PSL_ID_An_L (1ull << (63-30))
219 #define CXL_PSL_SERR_An_afuto (1ull << (63-0))
220 #define CXL_PSL_SERR_An_afudis (1ull << (63-1))
221 #define CXL_PSL_SERR_An_afuov (1ull << (63-2))
222 #define CXL_PSL_SERR_An_badsrc (1ull << (63-3))
223 #define CXL_PSL_SERR_An_badctx (1ull << (63-4))
224 #define CXL_PSL_SERR_An_llcmdis (1ull << (63-5))
225 #define CXL_PSL_SERR_An_llcmdto (1ull << (63-6))
226 #define CXL_PSL_SERR_An_afupar (1ull << (63-7))
227 #define CXL_PSL_SERR_An_afudup (1ull << (63-8))
232 #define CXL_PSL_SERR_An_afuto_mask (1ull << (63-32))
233 #define CXL_PSL_SERR_An_afudis_mask (1ull << (63-33))
234 #define CXL_PSL_SERR_An_afuov_mask (1ull << (63-34))
235 #define CXL_PSL_SERR_An_badsrc_mask (1ull << (63-35))
236 #define CXL_PSL_SERR_An_badctx_mask (1ull << (63-36))
237 #define CXL_PSL_SERR_An_llcmdis_mask (1ull << (63-37))
238 #define CXL_PSL_SERR_An_llcmdto_mask (1ull << (63-38))
239 #define CXL_PSL_SERR_An_afupar_mask (1ull << (63-39))
240 #define CXL_PSL_SERR_An_afudup_mask (1ull << (63-40))
246 #define CXL_PSL_SERR_An_AE (1ull << (63-30))
249 #define CXL_PSL_SCNTL_An_CR (0x1ull << (63-15))
251 #define CXL_PSL_SCNTL_An_PM_MASK (0xffffull << (63-31))
252 #define CXL_PSL_SCNTL_An_PM_Shared (0x0000ull << (63-31))
253 #define CXL_PSL_SCNTL_An_PM_OS (0x0001ull << (63-31))
254 #define CXL_PSL_SCNTL_An_PM_Process (0x0002ull << (63-31))
255 #define CXL_PSL_SCNTL_An_PM_AFU (0x0004ull << (63-31))
256 #define CXL_PSL_SCNTL_An_PM_AFU_PBT (0x0104ull << (63-31))
258 #define CXL_PSL_SCNTL_An_Ps_MASK (0x3ull << (63-39))
259 #define CXL_PSL_SCNTL_An_Ps_Pending (0x1ull << (63-39))
260 #define CXL_PSL_SCNTL_An_Ps_Complete (0x3ull << (63-39))
262 #define CXL_PSL_SCNTL_An_Pc (0x1ull << (63-48))
264 #define CXL_PSL_SCNTL_An_Ss_MASK (0x3ull << (63-55))
265 #define CXL_PSL_SCNTL_An_Ss_Pending (0x1ull << (63-55))
266 #define CXL_PSL_SCNTL_An_Ss_Complete (0x3ull << (63-55))
268 #define CXL_PSL_SCNTL_An_Sc (0x1ull << (63-63))
271 #define CXL_AFU_Cntl_An_ES_MASK (0x7ull << (63-2))
272 #define CXL_AFU_Cntl_An_ES_Disabled (0x0ull << (63-2))
273 #define CXL_AFU_Cntl_An_ES_Enabled (0x4ull << (63-2))
275 #define CXL_AFU_Cntl_An_E (0x1ull << (63-3))
277 #define CXL_AFU_Cntl_An_RS_MASK (0x3ull << (63-5))
278 #define CXL_AFU_Cntl_An_RS_Pending (0x1ull << (63-5))
279 #define CXL_AFU_Cntl_An_RS_Complete (0x2ull << (63-5))
281 #define CXL_AFU_Cntl_An_RA (0x1ull << (63-7))
286 #define CXL_SSTP0_An_KS (1ull << (63-2))
287 #define CXL_SSTP0_An_KP (1ull << (63-3))
288 #define CXL_SSTP0_An_N (1ull << (63-4))
289 #define CXL_SSTP0_An_L (1ull << (63-5))
290 #define CXL_SSTP0_An_C (1ull << (63-6))
291 #define CXL_SSTP0_An_TA (1ull << (63-7))
292 #define CXL_SSTP0_An_LP_SHIFT (63-9) /* 2 Bits */
294 #define CXL_SSTP0_An_SegTableSize_SHIFT (63-31) /* 12 Bits */
296 (((1ull << 12) - 1) << CXL_SSTP0_An_SegTableSize_SHIFT)
297 #define CXL_SSTP0_An_STVA_U_MASK ((1ull << (63-49))-1)
298 #define CXL_SSTP1_An_STVA_L_MASK (~((1ull << (63-55))-1))
299 #define CXL_SSTP1_An_V (1ull << (63-63))
301 /****** CXL_PSL_SLBIE_[An] - CAIA 1 **************************************************/
309 #define CXL_SLBIE_PENDING PPC_BITMASK(56, 63)
311 /****** Common to all CXL_TLBIA/SLBIA_[An] - CAIA 1 **********************************/
314 /****** Common to all CXL_TLB/SLB_IA/IE_[An] registers - CAIA 1 **********************/
315 #define CXL_TLB_SLB_IQ_ALL (0ull) /* Inv qualifier */
320 #define CXL_PSL_AFUSEL_A (1ull << (63-55)) /* Adapter wide invalidates affect all AFUs */
322 /****** CXL_PSL_DSISR_An - CAIA 1 ****************************************************/
323 #define CXL_PSL_DSISR_An_DS (1ull << (63-0)) /* Segment not found */
324 #define CXL_PSL_DSISR_An_DM (1ull << (63-1)) /* PTE not found (See also: M) or protection fault */
325 #define CXL_PSL_DSISR_An_ST (1ull << (63-2)) /* Segment Table PTE not found */
326 #define CXL_PSL_DSISR_An_UR (1ull << (63-3)) /* AURP PTE not found */
328 #define CXL_PSL_DSISR_An_PE (1ull << (63-4)) /* PSL Error (implementation specific) */
329 #define CXL_PSL_DSISR_An_AE (1ull << (63-5)) /* AFU Error */
330 #define CXL_PSL_DSISR_An_OC (1ull << (63-6)) /* OS Context Warning */
332 /* NOTE: Bits 32:63 are undefined if DSISR[DS] = 1 */
335 #define CXL_PSL_DSISR_An_A (1ull << (63-37)) /* AFU lock access to write through or cache inhibite…
339 /****** CXL_PSL_DSISR_An - CAIA 2 ****************************************************/
340 #define CXL_PSL9_DSISR_An_TF (1ull << (63-3)) /* Translation fault */
341 #define CXL_PSL9_DSISR_An_PE (1ull << (63-4)) /* PSL Error (implementation specific) */
342 #define CXL_PSL9_DSISR_An_AE (1ull << (63-5)) /* AFU Error */
343 #define CXL_PSL9_DSISR_An_OC (1ull << (63-6)) /* OS Context Warning */
344 #define CXL_PSL9_DSISR_An_S (1ull << (63-38)) /* TF for a write operation */
347 * NOTE: Bits 56:63 (Checkout Response Status) are valid when DSISR_An[TF] = 1
348 * Status (0:7) Encoding
350 #define CXL_PSL9_DSISR_An_CO_MASK 0x00000000000000ffULL
351 #define CXL_PSL9_DSISR_An_SF 0x0000000000000080ULL /* Segment Fault 0b…
352 #define CXL_PSL9_DSISR_An_PF_SLR 0x0000000000000088ULL /* PTE not found (Single Level Radix) 0b…
353 #define CXL_PSL9_DSISR_An_PF_RGC 0x000000000000008CULL /* PTE not found (Radix Guest (child)) 0b…
354 #define CXL_PSL9_DSISR_An_PF_RGP 0x0000000000000090ULL /* PTE not found (Radix Guest (parent)) 0b…
355 #define CXL_PSL9_DSISR_An_PF_HRH 0x0000000000000094ULL /* PTE not found (HPT/Radix Host) 0b…
356 #define CXL_PSL9_DSISR_An_PF_STEG 0x000000000000009CULL /* PTE not found (STEG VA) 0b…
357 #define CXL_PSL9_DSISR_An_URTCH 0x00000000000000B4ULL /* Unsupported Radix Tree Configuration 0b…
360 #define CXL_PSL_TFC_An_A (1ull << (63-28)) /* Acknowledge non-translation fault */
361 #define CXL_PSL_TFC_An_C (1ull << (63-29)) /* Continue (abort transaction) */
362 #define CXL_PSL_TFC_An_AE (1ull << (63-30)) /* Restart PSL with address error */
363 #define CXL_PSL_TFC_An_R (1ull << (63-31)) /* Restart PSL transaction */
366 #define CXL_PSL_DEBUG_CDC (1ull << (63-27)) /* Coherent Data cache support */
368 /****** CXL_XSL9_IERAT_ERAT - CAIA 2 **********************************/
369 #define CXL_XSL9_IERAT_MLPID (1ull << (63-0)) /* Match LPID */
370 #define CXL_XSL9_IERAT_MPID (1ull << (63-1)) /* Match PID */
371 #define CXL_XSL9_IERAT_PRS (1ull << (63-4)) /* PRS bit for Radix invalidations */
372 #define CXL_XSL9_IERAT_INVR (1ull << (63-3)) /* Invalidate Radix */
373 #define CXL_XSL9_IERAT_IALL (1ull << (63-8)) /* Invalidate All */
374 #define CXL_XSL9_IERAT_IINPROG (1ull << (63-63)) /* Invalidate in progress */
376 /* cxl_process_element->software_status */
377 #define CXL_PE_SOFTWARE_STATE_V (1ul << (31 - 0)) /* Valid */
378 #define CXL_PE_SOFTWARE_STATE_C (1ul << (31 - 29)) /* Complete */
379 #define CXL_PE_SOFTWARE_STATE_S (1ul << (31 - 30)) /* Suspend */
380 #define CXL_PE_SOFTWARE_STATE_T (1ul << (31 - 31)) /* Terminate */
387 #define CXL_PSL_RXCTL_AFUHP_4S 0x7000000000000000ULL
389 /* SPA->sw_command_status */
390 #define CXL_SPA_SW_CMD_MASK 0xffff000000000000ULL
391 #define CXL_SPA_SW_CMD_TERMINATE 0x0001000000000000ULL
392 #define CXL_SPA_SW_CMD_REMOVE 0x0002000000000000ULL
393 #define CXL_SPA_SW_CMD_SUSPEND 0x0003000000000000ULL
394 #define CXL_SPA_SW_CMD_RESUME 0x0004000000000000ULL
395 #define CXL_SPA_SW_CMD_ADD 0x0005000000000000ULL
396 #define CXL_SPA_SW_CMD_UPDATE 0x0006000000000000ULL
397 #define CXL_SPA_SW_STATE_MASK 0x0000ffff00000000ULL
398 #define CXL_SPA_SW_STATE_TERMINATED 0x0000000100000000ULL
399 #define CXL_SPA_SW_STATE_REMOVED 0x0000000200000000ULL
400 #define CXL_SPA_SW_STATE_SUSPENDED 0x0000000300000000ULL
401 #define CXL_SPA_SW_STATE_RESUMED 0x0000000400000000ULL
402 #define CXL_SPA_SW_STATE_ADDED 0x0000000500000000ULL
403 #define CXL_SPA_SW_STATE_UPDATED 0x0000000600000000ULL
404 #define CXL_SPA_SW_PSL_ID_MASK 0x00000000ffff0000ULL
405 #define CXL_SPA_SW_LINK_MASK 0x000000000000ffffULL
410 #define CXL_MODE_TIME_SLICED 0x4
414 #define CXL_CARD_MINOR(adapter) (adapter->adapter_num * CXL_DEV_MINORS)
417 #define CXL_PSL9_TRACEID_MAX 0xAU
418 #define CXL_PSL9_TRACESTATE_FIN 0x3U
497 /* -1: AFU deconfigured/locked, >= 0: number of readers */
597 * On bare-metal, pe=external_pe, because we decide what the handle is.
707 * >0: Number of contexts mapped and new one can be mapped.
708 * 0: No active contexts and new ones can be mapped.
709 * -1: No contexts mapped and new ones cannot be mapped.
724 /* common == phyp + powernv - CAIA 1&2 */
748 /* just powernv - CAIA 1&2 */
770 pdev = to_pci_dev(cxl->dev.parent); in cxl_adapter_link_ok()
779 return cxl->native->p1_mmio + cxl_reg_off(reg); in _cxl_p1_addr()
793 return ~0ULL; in cxl_p1_read()
799 return afu->native->p1n_mmio + cxl_reg_off(reg); in _cxl_p1n_addr()
804 if (likely(cxl_adapter_link_ok(afu->adapter, afu))) in cxl_p1n_write()
810 if (likely(cxl_adapter_link_ok(afu->adapter, afu))) in cxl_p1n_read()
813 return ~0ULL; in cxl_p1n_read()
818 return afu->p2n_mmio + cxl_reg_off(reg); in _cxl_p2n_addr()
823 if (likely(cxl_adapter_link_ok(afu->adapter, afu))) in cxl_p2n_write()
829 if (likely(cxl_adapter_link_ok(afu->adapter, afu))) in cxl_p2n_read()
832 return ~0ULL; in cxl_p2n_read()
995 * Field pid_tid is now 'reserved' because it's no more used on bare-metal.
1116 * In case an adapter_context_lock is taken the return -EBUSY.
1126 /* Unlock the contexts-lock if taken. Warn and force unlock otherwise */