1 // SPDX-License-Identifier: GPL-2.0
5  * Copyright (C) 2023 BayLibre Incorporated - https://www.baylibre.com/
127 	MFD_CELL_RES("tps6594-regulator", tps6594_regulator_resources),
128 	MFD_CELL_RES("tps6594-pinctrl", tps6594_pinctrl_resources),
129 	MFD_CELL_RES("tps6594-pfsm", tps6594_pfsm_resources),
130 	MFD_CELL_RES("tps6594-esm", tps6594_esm_resources),
134 	MFD_CELL_RES("tps6594-rtc", tps6594_rtc_resources),
339 	MFD_CELL_RES("tps65224-adc", tps65224_adc_resources),
340 	MFD_CELL_RES("tps6594-pfsm", tps65224_pfsm_resources),
341 	MFD_CELL_RES("tps6594-pinctrl", tps65224_pinctrl_resources),
342 	MFD_CELL_RES("tps6594-regulator", tps65224_regulator_resources),
436 	 * When CRC is enabled, writing to a read-only bit triggers an error,  in tps6594_handle_post_irq()
438 	 * (that must be cleared) and read-only bits are sometimes grouped in  in tps6594_handle_post_irq()
441 	 * an interrupt bit in a register containing also a read-only bit makes  in tps6594_handle_post_irq()
445 	if (tps->use_crc) {  in tps6594_handle_post_irq()
446 		if (tps->chip_id == TPS65224) {  in tps6594_handle_post_irq()
454 		ret = regmap_write_bits(tps->regmap, regmap_reg, mask_val, mask_val);  in tps6594_handle_post_irq()
510 	if (tps->chip_id == TPS65224) {  in tps6594_check_crc_mode()
522 	tps->use_crc = true;  in tps6594_check_crc_mode()
523 	ret = regmap_test_bits(tps->regmap, regmap_reg, mask_val);  in tps6594_check_crc_mode()
525 		ret = -EIO;  in tps6594_check_crc_mode()
527 		dev_info(tps->dev, "CRC feature enabled on %s PMIC",  in tps6594_check_crc_mode()
528 			 primary_pmic ? "primary" : "secondary");  in tps6594_check_crc_mode()
540 	if (tps->chip_id == TPS65224) {  in tps6594_set_crc_feature()
552 		 * on primary PMIC.  in tps6594_set_crc_feature()
554 		tps->use_crc = false;  in tps6594_set_crc_feature()
555 		ret = regmap_write_bits(tps->regmap, regmap_reg, mask_val, mask_val);  in tps6594_set_crc_feature()
561 		 * The datasheet indicates 2 ms, and clock specification is +/-5%.  in tps6594_set_crc_feature()
574 	struct device *dev = tps->dev;  in tps6594_enable_crc()
581 	 * If this mode is specified for primary PMIC, it will also be applied to secondary PMICs  in tps6594_enable_crc()
583 	 * In this multi-PMIC synchronization scheme, the primary PMIC is the controller device  in tps6594_enable_crc()
586 	is_primary = of_property_read_bool(dev->of_node, "ti,primary-pmic");  in tps6594_enable_crc()
588 		/* Enable CRC feature on primary PMIC */  in tps6594_enable_crc()
596 		/* Wait for CRC feature enabling event from primary PMIC */  in tps6594_enable_crc()
599 			ret = -ETIMEDOUT;  in tps6594_enable_crc()
609 	struct device *dev = tps->dev;  in tps6594_device_init()
621 	/* Keep PMIC in ACTIVE state */  in tps6594_device_init()
622 	ret = regmap_set_bits(tps->regmap, TPS6594_REG_FSM_NSLEEP_TRIGGERS,  in tps6594_device_init()
625 		return dev_err_probe(dev, ret, "Failed to set PMIC state\n");  in tps6594_device_init()
627 	if (tps->chip_id == TPS65224) {  in tps6594_device_init()
637 	irq_chip->irq_drv_data = tps;  in tps6594_device_init()
638 	irq_chip->name = devm_kasprintf(dev, GFP_KERNEL, "%s-%ld-0x%02x",  in tps6594_device_init()
639 					dev->driver->name, tps->chip_id, tps->reg);  in tps6594_device_init()
641 	if (!irq_chip->name)  in tps6594_device_init()
642 		return -ENOMEM;  in tps6594_device_init()
644 	ret = devm_regmap_add_irq_chip(dev, tps->regmap, tps->irq, IRQF_SHARED | IRQF_ONESHOT,  in tps6594_device_init()
645 				       0, irq_chip, &tps->irq_data);  in tps6594_device_init()
650 				   regmap_irq_get_domain(tps->irq_data));  in tps6594_device_init()
655 	if (tps->chip_id != LP8764 && tps->chip_id != TPS65224) {  in tps6594_device_init()
658 					   regmap_irq_get_domain(tps->irq_data));  in tps6594_device_init()