Lines Matching +full:0 +full:x8ff

23 #define TIMB_REV_MAJOR	0x00
24 #define TIMB_REV_MINOR	0x04
25 #define TIMB_HW_CONFIG	0x08
26 #define TIMB_SW_RST	0x40
29 #define TIMB_HW_CONFIG_SPI_8BIT	0x80
31 #define TIMB_HW_VER_MASK	0x0f
32 #define TIMB_HW_VER0		0x00
33 #define TIMB_HW_VER1		0x01
34 #define TIMB_HW_VER2		0x02
35 #define TIMB_HW_VER3		0x03
37 #define OCORESOFFSET	0x0
38 #define OCORESEND	0x1f
40 #define SPIOFFSET	0x80
41 #define SPIEND		0xff
43 #define UARTLITEOFFSET	0x100
44 #define UARTLITEEND	0x10f
46 #define RDSOFFSET	0x180
47 #define RDSEND		0x183
49 #define ETHOFFSET	0x300
50 #define ETHEND		0x3ff
52 #define GPIOOFFSET	0x400
53 #define GPIOEND		0x7ff
55 #define CHIPCTLOFFSET	0x800
56 #define CHIPCTLEND	0x8ff
59 #define INTCOFFSET	0xc00
60 #define INTCEND		0xfff
63 #define MOSTOFFSET	0x1000
64 #define MOSTEND		0x13ff
66 #define UARTOFFSET	0x1400
67 #define UARTEND		0x17ff
69 #define XIICOFFSET	0x1800
70 #define XIICEND		0x19ff
72 #define I2SOFFSET	0x1C00
73 #define I2SEND		0x1fff
75 #define LOGIWOFFSET	0x30000
76 #define LOGIWEND	0x37fff
78 #define MLCOREOFFSET	0x40000
79 #define MLCOREEND	0x43fff
81 #define DMAOFFSET	0x01000000
82 #define DMAEND		0x013fffff
85 #define SDHC0OFFSET	0x00
86 #define SDHC0END	0xff
89 #define SDHC1OFFSET	0x00
90 #define SDHC1END	0xff
92 #define PCI_VENDOR_ID_TIMB	0x10ee
93 #define PCI_DEVICE_ID_TIMB	0xa123
95 #define IRQ_TIMBERDALE_INIC		0
119 #define DMA_UART_RX         0