15 void m10bmc_fw_state_set(struct intel_m10bmc *m10bmc, enum m10bmc_fw_state new_state)  in m10bmc_fw_state_set()  argument
18 	if (!m10bmc->info->handshake_sys_reg_nranges)  in m10bmc_fw_state_set()
21 	down_write(&m10bmc->bmcfw_lock);  in m10bmc_fw_state_set()
22 	m10bmc->bmcfw_state = new_state;  in m10bmc_fw_state_set()
23 	up_write(&m10bmc->bmcfw_lock);  in m10bmc_fw_state_set()
31 static bool m10bmc_reg_always_available(struct intel_m10bmc *m10bmc, unsigned int offset)  in m10bmc_reg_always_available()  argument
33 	if (!m10bmc->info->handshake_sys_reg_nranges)  in m10bmc_reg_always_available()
36 	return !regmap_reg_in_ranges(offset, m10bmc->info->handshake_sys_reg_ranges,  in m10bmc_reg_always_available()
37 				     m10bmc->info->handshake_sys_reg_nranges);  in m10bmc_reg_always_available()
49 static bool m10bmc_handshake_reg_unavailable(struct intel_m10bmc *m10bmc)  in m10bmc_handshake_reg_unavailable()  argument
51 	return m10bmc->bmcfw_state == M10BMC_FW_STATE_SEC_UPDATE_PREPARE ||  in m10bmc_handshake_reg_unavailable()
52 	       m10bmc->bmcfw_state == M10BMC_FW_STATE_SEC_UPDATE_WRITE;  in m10bmc_handshake_reg_unavailable()
61 int m10bmc_sys_read(struct intel_m10bmc *m10bmc, unsigned int offset, unsigned int *val)  in m10bmc_sys_read()  argument
63 	const struct m10bmc_csr_map *csr_map = m10bmc->info->csr_map;  in m10bmc_sys_read()
66 	if (m10bmc_reg_always_available(m10bmc, offset))  in m10bmc_sys_read()
67 		return m10bmc_raw_read(m10bmc, csr_map->base + offset, val);  in m10bmc_sys_read()
69 	down_read(&m10bmc->bmcfw_lock);  in m10bmc_sys_read()
70 	if (m10bmc_handshake_reg_unavailable(m10bmc))  in m10bmc_sys_read()
73 		ret = m10bmc_raw_read(m10bmc, csr_map->base + offset, val);  in m10bmc_sys_read()
74 	up_read(&m10bmc->bmcfw_lock);  in m10bmc_sys_read()
80 int m10bmc_sys_update_bits(struct intel_m10bmc *m10bmc, unsigned int offset,  in m10bmc_sys_update_bits()  argument
83 	const struct m10bmc_csr_map *csr_map = m10bmc->info->csr_map;  in m10bmc_sys_update_bits()
86 	if (m10bmc_reg_always_available(m10bmc, offset))  in m10bmc_sys_update_bits()
87 		return regmap_update_bits(m10bmc->regmap, csr_map->base + offset, msk, val);  in m10bmc_sys_update_bits()
89 	down_read(&m10bmc->bmcfw_lock);  in m10bmc_sys_update_bits()
90 	if (m10bmc_handshake_reg_unavailable(m10bmc))  in m10bmc_sys_update_bits()
93 		ret = regmap_update_bits(m10bmc->regmap, csr_map->base + offset, msk, val);  in m10bmc_sys_update_bits()
94 	up_read(&m10bmc->bmcfw_lock);  in m10bmc_sys_update_bits()
188 int m10bmc_dev_init(struct intel_m10bmc *m10bmc, const struct intel_m10bmc_platform_info *info)  in m10bmc_dev_init()  argument
192 	m10bmc->info = info;  in m10bmc_dev_init()
193 	dev_set_drvdata(m10bmc->dev, m10bmc);  in m10bmc_dev_init()
194 	init_rwsem(&m10bmc->bmcfw_lock);  in m10bmc_dev_init()
196 	ret = devm_mfd_add_devices(m10bmc->dev, PLATFORM_DEVID_AUTO,  in m10bmc_dev_init()
200 		dev_err(m10bmc->dev, "Failed to register sub-devices: %d\n", ret);  in m10bmc_dev_init()