1 // SPDX-License-Identifier: GPL-2.0-only
3  * Copyright (C) 2014-2015 Pengutronix, Markus Pargmann <mpa@pengutronix.de>
6 #include <linux/clk.h>
12 #include <linux/mfd/imx25-tsadc.h>
35 	regmap_read(tsadc->regs, MX25_TSC_TGSR, &status);  in mx25_tsadc_irq_handler()
38 		generic_handle_domain_irq(tsadc->domain, 1);  in mx25_tsadc_irq_handler()
41 		generic_handle_domain_irq(tsadc->domain, 0);  in mx25_tsadc_irq_handler()
49 	struct mx25_tsadc *tsadc = d->host_data;  in mx25_tsadc_domain_map()
67 	struct device *dev = &pdev->dev;  in mx25_tsadc_setup_irq()
68 	struct device_node *np = dev->of_node;  in mx25_tsadc_setup_irq()
75 	tsadc->domain = irq_domain_add_simple(np, 2, 0, &mx25_tsadc_domain_ops,  in mx25_tsadc_setup_irq()
77 	if (!tsadc->domain) {  in mx25_tsadc_setup_irq()
79 		return -ENOMEM;  in mx25_tsadc_setup_irq()
94 		irq_domain_remove(tsadc->domain);  in mx25_tsadc_unset_irq()
106 	 * According to the datasheet the ADC clock should never  in mx25_tsadc_setup_clk()
107 	 * exceed 1,75 MHz. Base clock is the IPG and the ADC unit uses  in mx25_tsadc_setup_clk()
108 	 * a funny clock divider. To keep the ADC conversion time constant  in mx25_tsadc_setup_clk()
109 	 * adapt the ADC internal clock divider to the IPG clock rate.  in mx25_tsadc_setup_clk()
112 	dev_dbg(&pdev->dev, "Found master clock at %lu Hz\n",  in mx25_tsadc_setup_clk()
113 		clk_get_rate(tsadc->clk));  in mx25_tsadc_setup_clk()
115 	clk_div = DIV_ROUND_UP(clk_get_rate(tsadc->clk), 1750000);  in mx25_tsadc_setup_clk()
116 	dev_dbg(&pdev->dev, "Setting up ADC clock divider to %u\n", clk_div);  in mx25_tsadc_setup_clk()
118 	/* adc clock = IPG clock / (2 * div + 2) */  in mx25_tsadc_setup_clk()
119 	clk_div -= 2;  in mx25_tsadc_setup_clk()
123 	 * the ADC clock divider changes its behaviour when values below 4  in mx25_tsadc_setup_clk()
128 	dev_dbg(&pdev->dev, "Resulting ADC conversion clock at %lu Hz\n",  in mx25_tsadc_setup_clk()
129 		clk_get_rate(tsadc->clk) / (2 * clk_div + 2));  in mx25_tsadc_setup_clk()
131 	regmap_update_bits(tsadc->regs, MX25_TSC_TGCR,  in mx25_tsadc_setup_clk()
138 	struct device *dev = &pdev->dev;  in mx25_tsadc_probe()
145 		return -ENOMEM;  in mx25_tsadc_probe()
151 	tsadc->regs = devm_regmap_init_mmio(dev, iomem,  in mx25_tsadc_probe()
153 	if (IS_ERR(tsadc->regs)) {  in mx25_tsadc_probe()
155 		return PTR_ERR(tsadc->regs);  in mx25_tsadc_probe()
158 	tsadc->clk = devm_clk_get(dev, "ipg");  in mx25_tsadc_probe()
159 	if (IS_ERR(tsadc->clk)) {  in mx25_tsadc_probe()
161 		return PTR_ERR(tsadc->clk);  in mx25_tsadc_probe()
168 	regmap_update_bits(tsadc->regs, MX25_TSC_TGCR, MX25_TGCR_CLK_EN,  in mx25_tsadc_probe()
170 	regmap_update_bits(tsadc->regs, MX25_TSC_TGCR, MX25_TGCR_TSC_RST,  in mx25_tsadc_probe()
174 	regmap_update_bits(tsadc->regs, MX25_TSC_TGCR, MX25_TGCR_POWERMODE_MASK,  in mx25_tsadc_probe()
176 	regmap_update_bits(tsadc->regs, MX25_TSC_TGCR, MX25_TGCR_INTREFEN,  in mx25_tsadc_probe()
203 	{ .compatible = "fsl,imx25-tsadc" },
210 		.name = "mx25-tsadc",
218 MODULE_DESCRIPTION("MFD for ADC/TSC for Freescale mx25");
221 MODULE_ALIAS("platform:mx25-tsadc");