Lines Matching +full:0 +full:x03000000
88 U8 LUN[8]; /* 0Ch */
100 #define MPI_SCSIIO_MSGFLGS_SENSE_WIDTH (0x01)
101 #define MPI_SCSIIO_MSGFLGS_SENSE_WIDTH_32 (0x00)
102 #define MPI_SCSIIO_MSGFLGS_SENSE_WIDTH_64 (0x01)
104 #define MPI_SCSIIO_MSGFLGS_SENSE_LOCATION (0x02)
105 #define MPI_SCSIIO_MSGFLGS_SENSE_LOC_HOST (0x00)
106 #define MPI_SCSIIO_MSGFLGS_SENSE_LOC_IOC (0x02)
108 #define MPI_SCSIIO_MSGFLGS_CMD_DETERMINES_DATA_DIR (0x04)
112 #define MPI_SCSIIO_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF)
113 #define MPI_SCSIIO_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000)
114 #define MPI_SCSIIO_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF)
115 #define MPI_SCSIIO_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000)
116 #define MPI_SCSIIO_LUN_LEVEL_1_WORD (0xFF00)
117 #define MPI_SCSIIO_LUN_LEVEL_1_DWORD (0x0000FF00)
121 #define MPI_SCSIIO_CONTROL_DATADIRECTION_MASK (0x03000000)
122 #define MPI_SCSIIO_CONTROL_NODATATRANSFER (0x00000000)
123 #define MPI_SCSIIO_CONTROL_WRITE (0x01000000)
124 #define MPI_SCSIIO_CONTROL_READ (0x02000000)
126 #define MPI_SCSIIO_CONTROL_ADDCDBLEN_MASK (0x3C000000)
129 #define MPI_SCSIIO_CONTROL_TASKATTRIBUTE_MASK (0x00000700)
130 #define MPI_SCSIIO_CONTROL_SIMPLEQ (0x00000000)
131 #define MPI_SCSIIO_CONTROL_HEADOFQ (0x00000100)
132 #define MPI_SCSIIO_CONTROL_ORDEREDQ (0x00000200)
133 #define MPI_SCSIIO_CONTROL_ACAQ (0x00000400)
134 #define MPI_SCSIIO_CONTROL_UNTAGGED (0x00000500)
135 #define MPI_SCSIIO_CONTROL_NO_DISCONNECT (0x00000700)
137 #define MPI_SCSIIO_CONTROL_TASKMANAGE_MASK (0x00FF0000)
138 #define MPI_SCSIIO_CONTROL_OBSOLETE (0x00800000)
139 #define MPI_SCSIIO_CONTROL_CLEAR_ACA_RSV (0x00400000)
140 #define MPI_SCSIIO_CONTROL_TARGET_RESET (0x00200000)
141 #define MPI_SCSIIO_CONTROL_LUN_RESET_RSV (0x00100000)
142 #define MPI_SCSIIO_CONTROL_RESERVED (0x00080000)
143 #define MPI_SCSIIO_CONTROL_CLR_TASK_SET_RSV (0x00040000)
144 #define MPI_SCSIIO_CONTROL_ABORT_TASK_SET (0x00020000)
145 #define MPI_SCSIIO_CONTROL_RESERVED2 (0x00010000)
160 U8 SCSIStatus; /* 0Ch */
161 U8 SCSIState; /* 0Dh */
162 U16 IOCStatus; /* 0Eh */
175 #define MPI_SCSI_STATUS_SUCCESS (0x00)
176 #define MPI_SCSI_STATUS_CHECK_CONDITION (0x02)
177 #define MPI_SCSI_STATUS_CONDITION_MET (0x04)
178 #define MPI_SCSI_STATUS_BUSY (0x08)
179 #define MPI_SCSI_STATUS_INTERMEDIATE (0x10)
180 #define MPI_SCSI_STATUS_INTERMEDIATE_CONDMET (0x14)
181 #define MPI_SCSI_STATUS_RESERVATION_CONFLICT (0x18)
182 #define MPI_SCSI_STATUS_COMMAND_TERMINATED (0x22)
183 #define MPI_SCSI_STATUS_TASK_SET_FULL (0x28)
184 #define MPI_SCSI_STATUS_ACA_ACTIVE (0x30)
186 #define MPI_SCSI_STATUS_FCPEXT_DEVICE_LOGGED_OUT (0x80)
187 #define MPI_SCSI_STATUS_FCPEXT_NO_LINK (0x81)
188 #define MPI_SCSI_STATUS_FCPEXT_UNASSIGNED (0x82)
193 #define MPI_SCSI_STATE_AUTOSENSE_VALID (0x01)
194 #define MPI_SCSI_STATE_AUTOSENSE_FAILED (0x02)
195 #define MPI_SCSI_STATE_NO_SCSI_STATUS (0x04)
196 #define MPI_SCSI_STATE_TERMINATED (0x08)
197 #define MPI_SCSI_STATE_RESPONSE_INFO_VALID (0x10)
198 #define MPI_SCSI_STATE_QUEUE_TAG_REJECTED (0x20)
203 #define MPI_SCSI_RSP_INFO_FUNCTION_COMPLETE (0x00000000)
204 #define MPI_SCSI_RSP_INFO_FCP_BURST_LEN_ERROR (0x01000000)
205 #define MPI_SCSI_RSP_INFO_CMND_FIELDS_INVALID (0x02000000)
206 #define MPI_SCSI_RSP_INFO_FCP_DATA_RO_ERROR (0x03000000)
207 #define MPI_SCSI_RSP_INFO_TASK_MGMT_UNSUPPORTED (0x04000000)
208 #define MPI_SCSI_RSP_INFO_TASK_MGMT_FAILED (0x05000000)
209 #define MPI_SCSI_RSP_INFO_SPI_LQ_INVALID_TYPE (0x06000000)
211 #define MPI_SCSI_TASKTAG_UNKNOWN (0xFFFF)
275 U8 LUN[8]; /* 0Ch */
299 #define MPI_SCSIIO32_MSGFLGS_SENSE_WIDTH (0x01)
300 #define MPI_SCSIIO32_MSGFLGS_32_SENSE_WIDTH (0x00)
301 #define MPI_SCSIIO32_MSGFLGS_64_SENSE_WIDTH (0x01)
303 #define MPI_SCSIIO32_MSGFLGS_SENSE_LOCATION (0x02)
304 #define MPI_SCSIIO32_MSGFLGS_SENSE_LOC_HOST (0x00)
305 #define MPI_SCSIIO32_MSGFLGS_SENSE_LOC_IOC (0x02)
307 #define MPI_SCSIIO32_MSGFLGS_CMD_DETERMINES_DATA_DIR (0x04)
308 #define MPI_SCSIIO32_MSGFLGS_SGL_OFFSETS_CHAINS (0x08)
309 #define MPI_SCSIIO32_MSGFLGS_MULTICAST (0x10)
310 #define MPI_SCSIIO32_MSGFLGS_BIDIRECTIONAL (0x20)
311 #define MPI_SCSIIO32_MSGFLGS_LARGE_CDB (0x40)
314 #define MPI_SCSIIO32_FLAGS_FORM_MASK (0x03)
315 #define MPI_SCSIIO32_FLAGS_FORM_SCSIID (0x00)
316 #define MPI_SCSIIO32_FLAGS_FORM_WWID (0x01)
319 #define MPI_SCSIIO32_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF)
320 #define MPI_SCSIIO32_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000)
321 #define MPI_SCSIIO32_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF)
322 #define MPI_SCSIIO32_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000)
323 #define MPI_SCSIIO32_LUN_LEVEL_1_WORD (0xFF00)
324 #define MPI_SCSIIO32_LUN_LEVEL_1_DWORD (0x0000FF00)
327 #define MPI_SCSIIO32_CONTROL_DATADIRECTION_MASK (0x03000000)
328 #define MPI_SCSIIO32_CONTROL_NODATATRANSFER (0x00000000)
329 #define MPI_SCSIIO32_CONTROL_WRITE (0x01000000)
330 #define MPI_SCSIIO32_CONTROL_READ (0x02000000)
331 #define MPI_SCSIIO32_CONTROL_BIDIRECTIONAL (0x03000000)
333 #define MPI_SCSIIO32_CONTROL_ADDCDBLEN_MASK (0xFC000000)
336 #define MPI_SCSIIO32_CONTROL_TASKATTRIBUTE_MASK (0x00000700)
337 #define MPI_SCSIIO32_CONTROL_SIMPLEQ (0x00000000)
338 #define MPI_SCSIIO32_CONTROL_HEADOFQ (0x00000100)
339 #define MPI_SCSIIO32_CONTROL_ORDEREDQ (0x00000200)
340 #define MPI_SCSIIO32_CONTROL_ACAQ (0x00000400)
341 #define MPI_SCSIIO32_CONTROL_UNTAGGED (0x00000500)
342 #define MPI_SCSIIO32_CONTROL_NO_DISCONNECT (0x00000700)
344 #define MPI_SCSIIO32_CONTROL_TASKMANAGE_MASK (0x00FF0000)
345 #define MPI_SCSIIO32_CONTROL_OBSOLETE (0x00800000)
346 #define MPI_SCSIIO32_CONTROL_CLEAR_ACA_RSV (0x00400000)
347 #define MPI_SCSIIO32_CONTROL_TARGET_RESET (0x00200000)
348 #define MPI_SCSIIO32_CONTROL_LUN_RESET_RSV (0x00100000)
349 #define MPI_SCSIIO32_CONTROL_RESERVED (0x00080000)
350 #define MPI_SCSIIO32_CONTROL_CLR_TASK_SET_RSV (0x00040000)
351 #define MPI_SCSIIO32_CONTROL_ABORT_TASK_SET (0x00020000)
352 #define MPI_SCSIIO32_CONTROL_RESERVED2 (0x00010000)
355 #define MPI_SCSIIO32_EEDPFLAGS_MASK_OP (0x0007)
356 #define MPI_SCSIIO32_EEDPFLAGS_NOOP_OP (0x0000)
357 #define MPI_SCSIIO32_EEDPFLAGS_CHK_OP (0x0001)
358 #define MPI_SCSIIO32_EEDPFLAGS_STRIP_OP (0x0002)
359 #define MPI_SCSIIO32_EEDPFLAGS_CHKRM_OP (0x0003)
360 #define MPI_SCSIIO32_EEDPFLAGS_INSERT_OP (0x0004)
361 #define MPI_SCSIIO32_EEDPFLAGS_REPLACE_OP (0x0006)
362 #define MPI_SCSIIO32_EEDPFLAGS_CHKREGEN_OP (0x0007)
364 #define MPI_SCSIIO32_EEDPFLAGS_PASS_REF_TAG (0x0008)
365 #define MPI_SCSIIO32_EEDPFLAGS_8_9THS_MODE (0x0010)
367 #define MPI_SCSIIO32_EEDPFLAGS_T10_CHK_MASK (0x0700)
368 #define MPI_SCSIIO32_EEDPFLAGS_T10_CHK_GUARD (0x0100)
369 #define MPI_SCSIIO32_EEDPFLAGS_T10_CHK_REFTAG (0x0200)
370 #define MPI_SCSIIO32_EEDPFLAGS_T10_CHK_LBATAG (0x0400)
373 #define MPI_SCSIIO32_EEDPFLAGS_INC_SEC_APPTAG (0x1000)
374 #define MPI_SCSIIO32_EEDPFLAGS_INC_PRI_APPTAG (0x2000)
375 #define MPI_SCSIIO32_EEDPFLAGS_INC_SEC_REFTAG (0x4000)
376 #define MPI_SCSIIO32_EEDPFLAGS_INC_PRI_REFTAG (0x8000)
391 U8 SCSIStatus; /* 0Ch */
392 U8 SCSIState; /* 0Dh */
393 U16 IOCStatus; /* 0Eh */
420 U8 LUN[8]; /* 0Ch */
428 #define MPI_SCSITASKMGMT_TASKTYPE_ABORT_TASK (0x01)
429 #define MPI_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET (0x02)
430 #define MPI_SCSITASKMGMT_TASKTYPE_TARGET_RESET (0x03)
431 #define MPI_SCSITASKMGMT_TASKTYPE_RESET_BUS (0x04)
432 #define MPI_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET (0x05)
433 #define MPI_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET (0x06)
434 #define MPI_SCSITASKMGMT_TASKTYPE_QUERY_TASK (0x07)
435 #define MPI_SCSITASKMGMT_TASKTYPE_CLR_ACA (0x08)
438 #define MPI_SCSITASKMGMT_MSGFLAGS_DO_NOT_SEND_TASK_IU (0x01)
440 #define MPI_SCSITASKMGMT_MSGFLAGS_TARGET_RESET_OPTION (0x00)
441 #define MPI_SCSITASKMGMT_MSGFLAGS_LIP_RESET_OPTION (0x02)
442 #define MPI_SCSITASKMGMT_MSGFLAGS_LIPRESET_RESET_OPTION (0x04)
444 #define MPI_SCSITASKMGMT_MSGFLAGS_SOFT_RESET_OPTION (0x08)
458 U8 Reserved2[2]; /* 0Ch */
459 U16 IOCStatus; /* 0Eh */
466 #define MPI_SCSITASKMGMT_RSP_TM_COMPLETE (0x00)
467 #define MPI_SCSITASKMGMT_RSP_INVALID_FRAME (0x02)
468 #define MPI_SCSITASKMGMT_RSP_TM_NOT_SUPPORTED (0x04)
469 #define MPI_SCSITASKMGMT_RSP_TM_FAILED (0x05)
470 #define MPI_SCSITASKMGMT_RSP_TM_SUCCEEDED (0x08)
471 #define MPI_SCSITASKMGMT_RSP_TM_INVALID_LUN (0x09)
472 #define MPI_SCSITASKMGMT_RSP_IO_QUEUED_ON_IOC (0x80)
490 U32 SlotStatus; /* 0Ch */
500 #define MPI_SEP_REQ_ACTION_WRITE_STATUS (0x00)
501 #define MPI_SEP_REQ_ACTION_READ_STATUS (0x01)
504 #define MPI_SEP_REQ_FLAGS_ENCLOSURE_SLOT_ADDRESS (0x01)
505 #define MPI_SEP_REQ_FLAGS_BUS_TARGETID_ADDRESS (0x00)
508 #define MPI_SEP_REQ_SLOTSTATUS_NO_ERROR (0x00000001)
509 #define MPI_SEP_REQ_SLOTSTATUS_DEV_FAULTY (0x00000002)
510 #define MPI_SEP_REQ_SLOTSTATUS_DEV_REBUILDING (0x00000004)
511 #define MPI_SEP_REQ_SLOTSTATUS_IN_FAILED_ARRAY (0x00000008)
512 #define MPI_SEP_REQ_SLOTSTATUS_IN_CRITICAL_ARRAY (0x00000010)
513 #define MPI_SEP_REQ_SLOTSTATUS_PARITY_CHECK (0x00000020)
514 #define MPI_SEP_REQ_SLOTSTATUS_PREDICTED_FAULT (0x00000040)
515 #define MPI_SEP_REQ_SLOTSTATUS_UNCONFIGURED (0x00000080)
516 #define MPI_SEP_REQ_SLOTSTATUS_HOT_SPARE (0x00000100)
517 #define MPI_SEP_REQ_SLOTSTATUS_REBUILD_STOPPED (0x00000200)
518 #define MPI_SEP_REQ_SLOTSTATUS_REQ_CONSISTENCY_CHECK (0x00001000)
519 #define MPI_SEP_REQ_SLOTSTATUS_DISABLE (0x00002000)
520 #define MPI_SEP_REQ_SLOTSTATUS_REQ_RESERVED_DEVICE (0x00004000)
521 #define MPI_SEP_REQ_SLOTSTATUS_IDENTIFY_REQUEST (0x00020000)
522 #define MPI_SEP_REQ_SLOTSTATUS_REQUEST_REMOVE (0x00040000)
523 #define MPI_SEP_REQ_SLOTSTATUS_REQUEST_INSERT (0x00080000)
524 #define MPI_SEP_REQ_SLOTSTATUS_DO_NOT_MOVE (0x00400000)
525 #define MPI_SEP_REQ_SLOTSTATUS_ACTIVE (0x00800000)
526 #define MPI_SEP_REQ_SLOTSTATUS_B_ENABLE_BYPASS (0x04000000)
527 #define MPI_SEP_REQ_SLOTSTATUS_A_ENABLE_BYPASS (0x08000000)
528 #define MPI_SEP_REQ_SLOTSTATUS_DEV_OFF (0x10000000)
529 #define MPI_SEP_REQ_SLOTSTATUS_SWAP_RESET (0x80000000)
543 U16 Reserved3; /* 0Ch */
544 U16 IOCStatus; /* 0Eh */
554 #define MPI_SEP_REPLY_SLOTSTATUS_NO_ERROR (0x00000001)
555 #define MPI_SEP_REPLY_SLOTSTATUS_DEV_FAULTY (0x00000002)
556 #define MPI_SEP_REPLY_SLOTSTATUS_DEV_REBUILDING (0x00000004)
557 #define MPI_SEP_REPLY_SLOTSTATUS_IN_FAILED_ARRAY (0x00000008)
558 #define MPI_SEP_REPLY_SLOTSTATUS_IN_CRITICAL_ARRAY (0x00000010)
559 #define MPI_SEP_REPLY_SLOTSTATUS_PARITY_CHECK (0x00000020)
560 #define MPI_SEP_REPLY_SLOTSTATUS_PREDICTED_FAULT (0x00000040)
561 #define MPI_SEP_REPLY_SLOTSTATUS_UNCONFIGURED (0x00000080)
562 #define MPI_SEP_REPLY_SLOTSTATUS_HOT_SPARE (0x00000100)
563 #define MPI_SEP_REPLY_SLOTSTATUS_REBUILD_STOPPED (0x00000200)
564 #define MPI_SEP_REPLY_SLOTSTATUS_CONSISTENCY_CHECK (0x00001000)
565 #define MPI_SEP_REPLY_SLOTSTATUS_DISABLE (0x00002000)
566 #define MPI_SEP_REPLY_SLOTSTATUS_RESERVED_DEVICE (0x00004000)
567 #define MPI_SEP_REPLY_SLOTSTATUS_REPORT (0x00010000)
568 #define MPI_SEP_REPLY_SLOTSTATUS_IDENTIFY_REQUEST (0x00020000)
569 #define MPI_SEP_REPLY_SLOTSTATUS_REMOVE_READY (0x00040000)
570 #define MPI_SEP_REPLY_SLOTSTATUS_INSERT_READY (0x00080000)
571 #define MPI_SEP_REPLY_SLOTSTATUS_DO_NOT_REMOVE (0x00400000)
572 #define MPI_SEP_REPLY_SLOTSTATUS_ACTIVE (0x00800000)
573 #define MPI_SEP_REPLY_SLOTSTATUS_B_BYPASS_ENABLED (0x01000000)
574 #define MPI_SEP_REPLY_SLOTSTATUS_A_BYPASS_ENABLED (0x02000000)
575 #define MPI_SEP_REPLY_SLOTSTATUS_B_ENABLE_BYPASS (0x04000000)
576 #define MPI_SEP_REPLY_SLOTSTATUS_A_ENABLE_BYPASS (0x08000000)
577 #define MPI_SEP_REPLY_SLOTSTATUS_DEV_OFF (0x10000000)
578 #define MPI_SEP_REPLY_SLOTSTATUS_FAULT_SENSED (0x40000000)
579 #define MPI_SEP_REPLY_SLOTSTATUS_SWAPPED (0x80000000)