drivers/memory/ti-emif-sram-pm.S

47 	ldr	r2, [r4, #EMIF_PM_REGS_VIRT_OFFSET]
51 	str	r1, [r2, #EMIF_SDCFG_VAL_OFFSET]
54 	str	r1, [r2, #EMIF_REF_CTRL_VAL_OFFSET]
57 	str     r1, [r2, #EMIF_TIMING1_VAL_OFFSET]
60 	str     r1, [r2, #EMIF_TIMING2_VAL_OFFSET]
63 	str     r1, [r2, #EMIF_TIMING3_VAL_OFFSET]
66 	str     r1, [r2, #EMIF_PMCR_VAL_OFFSET]
69 	str     r1, [r2, #EMIF_PMCR_SHDW_VAL_OFFSET]
72 	str     r1, [r2, #EMIF_ZQCFG_VAL_OFFSET]
75 	str     r1, [r2, #EMIF_DDR_PHY_CTLR_1_OFFSET]
78 	str     r1, [r2, #EMIF_COS_CONFIG_OFFSET]
81 	str     r1, [r2, #EMIF_PRIORITY_TO_COS_MAPPING_OFFSET]
84 	str     r1, [r2, #EMIF_CONNECT_ID_SERV_1_MAP_OFFSET]
87 	str     r1, [r2, #EMIF_CONNECT_ID_SERV_2_MAP_OFFSET]
90 	str     r1, [r2, #EMIF_OCP_CONFIG_VAL_OFFSET]
97 	str     r1, [r2, #EMIF_RD_WR_LEVEL_RAMP_CTRL_OFFSET]
100 	str     r1, [r2, #EMIF_RD_WR_EXEC_THRESH_OFFSET]
103 	str     r1, [r2, #EMIF_LPDDR2_NVM_TIM_OFFSET]
106 	str     r1, [r2, #EMIF_LPDDR2_NVM_TIM_SHDW_OFFSET]
109 	str     r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_OFFSET]
112 	str     r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_SHDW_OFFSET]
116 	add	r4, r2, #EMIF_EXT_PHY_CTRL_VALS_OFFSET
139 	ldr	r2, [r4, #EMIF_PM_REGS_PHYS_OFFSET]
142 	ldr     r1, [r2, #EMIF_DDR_PHY_CTLR_1_OFFSET]
146 	ldr     r1, [r2, #EMIF_TIMING1_VAL_OFFSET]
150 	ldr     r1, [r2, #EMIF_TIMING2_VAL_OFFSET]
154 	ldr     r1, [r2, #EMIF_TIMING3_VAL_OFFSET]
158 	ldr     r1, [r2, #EMIF_REF_CTRL_VAL_OFFSET]
162 	ldr     r1, [r2, #EMIF_PMCR_VAL_OFFSET]
165 	ldr     r1, [r2, #EMIF_PMCR_SHDW_VAL_OFFSET]
168 	ldr     r1, [r2, #EMIF_COS_CONFIG_OFFSET]
171 	ldr     r1, [r2, #EMIF_PRIORITY_TO_COS_MAPPING_OFFSET]
174 	ldr	r1, [r2, #EMIF_CONNECT_ID_SERV_1_MAP_OFFSET]
177 	ldr     r1, [r2, #EMIF_CONNECT_ID_SERV_2_MAP_OFFSET]
180 	ldr     r1, [r2, #EMIF_OCP_CONFIG_VAL_OFFSET]
187 	ldr     r1, [r2, #EMIF_RD_WR_LEVEL_RAMP_CTRL_OFFSET]
190 	ldr     r1, [r2, #EMIF_RD_WR_EXEC_THRESH_OFFSET]
193 	ldr     r1, [r2, #EMIF_LPDDR2_NVM_TIM_OFFSET]
196 	ldr     r1, [r2, #EMIF_LPDDR2_NVM_TIM_SHDW_OFFSET]
199 	ldr     r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_OFFSET]
202 	ldr     r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_SHDW_OFFSET]
205 	ldr     r1, [r2, #EMIF_ZQCFG_VAL_OFFSET]
213 	add	r3, r2, #EMIF_EXT_PHY_CTRL_VALS_OFFSET
229 	ldr     r1, [r2, #EMIF_ZQCFG_VAL_OFFSET]
233 	ldr	r1, [r2, #EMIF_SDCFG_VAL_OFFSET]
234 	and	r2, r1, #SDRAM_TYPE_MASK
235 	cmp	r2, #EMIF_SDCFG_TYPE_DDR2
253 	ldr	r2, [r0, #EMIF_SDRAM_CONFIG]
254 	and	r2, r2, #SDRAM_TYPE_MASK
255 	cmp	r2, #EMIF_SDCFG_TYPE_DDR3
267 	mov	r2, #0x2000
269 	subs	r2, r2, #0x1
293 	ldr	r2, [r4, #EMIF_PM_REGS_VIRT_OFFSET]
313 	ldr	r2, [r4, #EMIF_PM_REGS_PHYS_OFFSET]
323 	ldr	r1, [r2, #EMIF_PMCR_VAL_OFFSET]
350 	ldr	r2, [r4, #EMIF_PM_REGS_VIRT_OFFSET]
352 	ldr	r1, [r2, #EMIF_PMCR_VAL_OFFSET]