44 #define EMC_CFG					0x00c  macro
370 	u32 emc_cfg;  member
554 	emc->emc_cfg = readl_relaxed(emc->regs + EMC_CFG);  in emc_prepare_timing_change()
577 	if (emc->emc_cfg & EMC_CFG_DYN_SREF_ENABLE) {  in emc_prepare_timing_change()
578 		emc->emc_cfg &= ~EMC_CFG_DYN_SREF_ENABLE;  in emc_prepare_timing_change()
579 		writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG);  in emc_prepare_timing_change()
691 		writel_relaxed(emc->emc_cfg | EMC_CFG_PERIODIC_QRST,  in emc_prepare_timing_change()
692 			       emc->regs + EMC_CFG);  in emc_prepare_timing_change()
719 	val = !!(emc->emc_cfg & EMC_CFG_PERIODIC_QRST);  in emc_prepare_timing_change()
722 			emc->emc_cfg |= EMC_CFG_PERIODIC_QRST;  in emc_prepare_timing_change()
724 			emc->emc_cfg &= ~EMC_CFG_PERIODIC_QRST;  in emc_prepare_timing_change()
726 		writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG);  in emc_prepare_timing_change()
820 		emc->emc_cfg |= EMC_CFG_DYN_SREF_ENABLE;  in emc_complete_timing_change()
821 		writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG);  in emc_complete_timing_change()
1117 	u32 fbio_cfg5, emc_cfg, emc_dbg, emc_adr_cfg;  in emc_setup_hw()  local
1127 	emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2);  in emc_setup_hw()
1130 	emc_cfg |= EMC_CLKCHANGE_REQ_ENABLE;  in emc_setup_hw()
1135 		emc_cfg |= EMC_CLKCHANGE_PD_ENABLE;  in emc_setup_hw()
1136 		emc_cfg &= ~EMC_CLKCHANGE_SR_ENABLE;  in emc_setup_hw()
1140 		emc_cfg &= ~EMC_CLKCHANGE_SR_ENABLE;  in emc_setup_hw()
1141 		emc_cfg &= ~EMC_CLKCHANGE_PD_ENABLE;  in emc_setup_hw()
1145 	writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2);  in emc_setup_hw()