Lines Matching +full:mc +full:- +full:sid
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2022-2023, NVIDIA CORPORATION. All rights reserved.
6 #include <soc/tegra/mc.h>
8 #include <dt-bindings/memory/tegra234-mc.h>
10 #include <linux/tegra-icc.h>
13 #include "mc.h"
16 * MC Client entries are sorted in the increasing order of the
25 .sid = TEGRA234_SID_HDA,
27 .sid = {
37 .sid = TEGRA234_SID_NVENC,
39 .sid = {
49 .sid = TEGRA234_SID_PCIE6,
51 .sid = {
61 .sid = TEGRA234_SID_PCIE6,
63 .sid = {
73 .sid = TEGRA234_SID_PCIE7,
75 .sid = {
85 .sid = TEGRA234_SID_NVENC,
87 .sid = {
97 .sid = TEGRA234_SID_NVDLA0,
99 .sid = {
109 .sid = TEGRA234_SID_NVDLA0,
111 .sid = {
121 .sid = TEGRA234_SID_NVDLA0,
123 .sid = {
133 .sid = TEGRA234_SID_NVDLA1,
135 .sid = {
145 .sid = TEGRA234_SID_PCIE7,
147 .sid = {
157 .sid = TEGRA234_SID_PCIE8,
159 .sid = {
169 .sid = TEGRA234_SID_HDA,
171 .sid = {
181 .sid = TEGRA234_SID_PCIE8,
183 .sid = {
193 .sid = TEGRA234_SID_PCIE9,
195 .sid = {
205 .sid = TEGRA234_SID_PCIE6,
207 .sid = {
217 .sid = TEGRA234_SID_PCIE9,
219 .sid = {
229 .sid = TEGRA234_SID_PCIE10,
231 .sid = {
241 .sid = TEGRA234_SID_PCIE10,
243 .sid = {
253 .sid = TEGRA234_SID_PCIE10,
255 .sid = {
265 .sid = TEGRA234_SID_PCIE7,
267 .sid = {
277 .sid = TEGRA234_SID_MGBE,
279 .sid = {
289 .sid = TEGRA234_SID_MGBE_VF1,
291 .sid = {
301 .sid = TEGRA234_SID_MGBE_VF2,
303 .sid = {
313 .sid = TEGRA234_SID_MGBE_VF3,
315 .sid = {
325 .sid = TEGRA234_SID_MGBE,
327 .sid = {
337 .sid = TEGRA234_SID_MGBE_VF1,
339 .sid = {
349 .sid = TEGRA234_SID_MGBE_VF2,
351 .sid = {
361 .sid = TEGRA234_SID_SDMMC4,
363 .sid = {
373 .sid = TEGRA234_SID_MGBE_VF3,
375 .sid = {
385 .sid = TEGRA234_SID_SDMMC4,
387 .sid = {
397 .sid = TEGRA234_SID_VIC,
399 .sid = {
409 .sid = TEGRA234_SID_VIC,
411 .sid = {
421 .sid = TEGRA234_SID_NVDLA1,
423 .sid = {
433 .sid = TEGRA234_SID_NVDLA1,
435 .sid = {
445 .sid = TEGRA234_SID_ISO_VI2,
447 .sid = {
457 .sid = TEGRA234_SID_ISO_VI2FALC,
459 .sid = {
469 .sid = TEGRA234_SID_ISO_VI,
471 .sid = {
481 .sid = TEGRA234_SID_NVDEC,
483 .sid = {
493 .sid = TEGRA234_SID_NVDEC,
495 .sid = {
505 .sid = TEGRA234_SID_APE,
507 .sid = {
517 .sid = TEGRA234_SID_APE,
519 .sid = {
529 .sid = TEGRA234_SID_ISO_VI2FALC,
531 .sid = {
541 .sid = TEGRA234_SID_NVJPG,
543 .sid = {
553 .sid = TEGRA234_SID_NVJPG,
555 .sid = {
565 .sid = TEGRA234_SID_ISO_NVDISPLAY,
567 .sid = {
575 .sid = TEGRA234_SID_BPMP,
577 .sid = {
585 .sid = TEGRA234_SID_BPMP,
587 .sid = {
595 .sid = TEGRA234_SID_BPMP,
597 .sid = {
605 .sid = TEGRA234_SID_BPMP,
607 .sid = {
617 .sid = TEGRA234_SID_APE,
619 .sid = {
629 .sid = TEGRA234_SID_APE,
631 .sid = {
641 .sid = TEGRA234_SID_ISO_NVDISPLAY,
643 .sid = {
653 .sid = TEGRA234_SID_ISO_VIFALC,
655 .sid = {
665 .sid = TEGRA234_SID_ISO_VIFALC,
667 .sid = {
677 .sid = TEGRA234_SID_NVDLA0,
679 .sid = {
689 .sid = TEGRA234_SID_NVDLA0,
691 .sid = {
701 .sid = TEGRA234_SID_NVDLA0,
703 .sid = {
713 .sid = TEGRA234_SID_NVDLA0,
715 .sid = {
725 .sid = TEGRA234_SID_NVDLA1,
727 .sid = {
737 .sid = TEGRA234_SID_NVDLA1,
739 .sid = {
749 .sid = TEGRA234_SID_NVDLA1,
751 .sid = {
761 .sid = TEGRA234_SID_NVDLA1,
763 .sid = {
773 .sid = TEGRA234_SID_RCE,
775 .sid = {
785 .sid = TEGRA234_SID_RCE,
787 .sid = {
797 .sid = TEGRA234_SID_PCIE0,
799 .sid = {
809 .sid = TEGRA234_SID_PCIE0,
811 .sid = {
821 .sid = TEGRA234_SID_PCIE1,
823 .sid = {
833 .sid = TEGRA234_SID_PCIE1,
835 .sid = {
845 .sid = TEGRA234_SID_PCIE2,
847 .sid = {
857 .sid = TEGRA234_SID_PCIE2,
859 .sid = {
869 .sid = TEGRA234_SID_PCIE3,
871 .sid = {
881 .sid = TEGRA234_SID_PCIE3,
883 .sid = {
893 .sid = TEGRA234_SID_PCIE4,
895 .sid = {
905 .sid = TEGRA234_SID_PCIE4,
907 .sid = {
917 .sid = TEGRA234_SID_PCIE5,
919 .sid = {
929 .sid = TEGRA234_SID_PCIE5,
931 .sid = {
941 .sid = TEGRA234_SID_NVDLA0,
943 .sid = {
951 .sid = TEGRA234_SID_NVDLA1,
953 .sid = {
963 .sid = TEGRA234_SID_PCIE5,
965 .sid = {
975 .sid = TEGRA234_SID_NVJPG1,
977 .sid = {
987 .sid = TEGRA234_SID_NVJPG1,
989 .sid = {
1023 * tegra234_mc_icc_set() - Pass MC client info to the BPMP-FW
1024 * @src: ICC node for Memory Controller's (MC) Client
1025 * @dst: ICC node for Memory Controller (MC)
1027 * Passing the current request info from the MC to the BPMP-FW where
1030 * icc_set_bw() makes set_bw calls for both MC and EMC providers in
1037 struct tegra_mc *mc = icc_provider_to_tegra_mc(dst->provider); in tegra234_mc_icc_set() local
1040 const struct tegra_mc_client *pclient = src->data; in tegra234_mc_icc_set()
1046 * This can be used to pre-initialize and set bandwidth for all clients in tegra234_mc_icc_set()
1048 * the pre-initialization already happened in Bootloader(MB2) and BPMP-FW. in tegra234_mc_icc_set()
1050 if (src->id == dst->id) in tegra234_mc_icc_set()
1053 if (!mc->bwmgr_mrq_supported) in tegra234_mc_icc_set()
1056 if (!mc->bpmp) { in tegra234_mc_icc_set()
1057 dev_err(mc->dev, "BPMP reference NULL\n"); in tegra234_mc_icc_set()
1058 return -ENOENT; in tegra234_mc_icc_set()
1061 if (pclient->type == TEGRA_ICC_NISO) in tegra234_mc_icc_set()
1062 bwmgr_req.bwmgr_calc_set_req.niso_bw = src->avg_bw; in tegra234_mc_icc_set()
1064 bwmgr_req.bwmgr_calc_set_req.iso_bw = src->avg_bw; in tegra234_mc_icc_set()
1066 bwmgr_req.bwmgr_calc_set_req.client_id = pclient->bpmp_id; in tegra234_mc_icc_set()
1069 bwmgr_req.bwmgr_calc_set_req.mc_floor = src->peak_bw; in tegra234_mc_icc_set()
1079 if (pclient->bpmp_id >= TEGRA_ICC_BPMP_CPU_CLUSTER0 && in tegra234_mc_icc_set()
1080 pclient->bpmp_id <= TEGRA_ICC_BPMP_CPU_CLUSTER2) in tegra234_mc_icc_set()
1083 ret = tegra_bpmp_transfer(mc->bpmp, &msg); in tegra234_mc_icc_set()
1085 dev_err(mc->dev, "BPMP transfer failed: %d\n", ret); in tegra234_mc_icc_set()
1091 ret = -EINVAL; in tegra234_mc_icc_set()
1101 struct icc_provider *p = node->provider; in tegra234_mc_icc_aggregate()
1102 struct tegra_mc *mc = icc_provider_to_tegra_mc(p); in tegra234_mc_icc_aggregate() local
1104 if (!mc->bwmgr_mrq_supported) in tegra234_mc_icc_aggregate()
1107 if (node->id == TEGRA_ICC_MC_CPU_CLUSTER0 || in tegra234_mc_icc_aggregate()
1108 node->id == TEGRA_ICC_MC_CPU_CLUSTER1 || in tegra234_mc_icc_aggregate()
1109 node->id == TEGRA_ICC_MC_CPU_CLUSTER2) { in tegra234_mc_icc_aggregate()
1110 if (mc) in tegra234_mc_icc_aggregate()
1111 peak_bw = peak_bw * mc->num_channels; in tegra234_mc_icc_aggregate()