Lines Matching +full:0 +full:x3c8
12 .id = 0x00,
16 .id = 0x01,
21 .reg = 0x228,
25 .reg = 0x2e8,
26 .shift = 0,
27 .mask = 0xff,
28 .def = 0x1e,
32 .id = 0x02,
37 .reg = 0x228,
41 .reg = 0x2f4,
42 .shift = 0,
43 .mask = 0xff,
44 .def = 0x1e,
48 .id = 0x03,
53 .reg = 0x228,
57 .reg = 0x2e8,
59 .mask = 0xff,
60 .def = 0x1e,
64 .id = 0x04,
69 .reg = 0x228,
73 .reg = 0x2f4,
75 .mask = 0xff,
76 .def = 0x1e,
80 .id = 0x05,
85 .reg = 0x228,
89 .reg = 0x2ec,
90 .shift = 0,
91 .mask = 0xff,
92 .def = 0x1e,
96 .id = 0x06,
101 .reg = 0x228,
105 .reg = 0x2f8,
106 .shift = 0,
107 .mask = 0xff,
108 .def = 0x1e,
112 .id = 0x0e,
117 .reg = 0x228,
121 .reg = 0x2e0,
122 .shift = 0,
123 .mask = 0xff,
124 .def = 0x2e,
128 .id = 0x0f,
133 .reg = 0x228,
137 .reg = 0x2e4,
138 .shift = 0,
139 .mask = 0xff,
140 .def = 0x04,
144 .id = 0x10,
149 .reg = 0x228,
153 .reg = 0x2f0,
154 .shift = 0,
155 .mask = 0xff,
156 .def = 0x1e,
160 .id = 0x11,
165 .reg = 0x228,
169 .reg = 0x2fc,
170 .shift = 0,
171 .mask = 0xff,
172 .def = 0x1e,
176 .id = 0x15,
181 .reg = 0x228,
185 .reg = 0x318,
186 .shift = 0,
187 .mask = 0xff,
188 .def = 0x24,
192 .id = 0x16,
197 .reg = 0x228,
201 .reg = 0x310,
202 .shift = 0,
203 .mask = 0xff,
204 .def = 0x1e,
208 .id = 0x17,
213 .reg = 0x228,
217 .reg = 0x310,
219 .mask = 0xff,
220 .def = 0x50,
224 .id = 0x1c,
229 .reg = 0x228,
233 .reg = 0x328,
234 .shift = 0,
235 .mask = 0xff,
236 .def = 0x23,
240 .id = 0x1d,
245 .reg = 0x228,
249 .reg = 0x344,
250 .shift = 0,
251 .mask = 0xff,
252 .def = 0x49,
256 .id = 0x1e,
261 .reg = 0x228,
265 .reg = 0x344,
267 .mask = 0xff,
268 .def = 0x1a,
272 .id = 0x1f,
277 .reg = 0x228,
281 .reg = 0x350,
282 .shift = 0,
283 .mask = 0xff,
284 .def = 0x65,
288 .id = 0x27,
293 .reg = 0x320,
294 .shift = 0,
295 .mask = 0xff,
296 .def = 0x04,
300 .id = 0x2b,
305 .reg = 0x22c,
309 .reg = 0x328,
311 .mask = 0xff,
312 .def = 0x80,
316 .id = 0x31,
321 .reg = 0x22c,
325 .reg = 0x2e0,
327 .mask = 0xff,
328 .def = 0x80,
332 .id = 0x32,
337 .reg = 0x22c,
341 .reg = 0x2e4,
343 .mask = 0xff,
344 .def = 0x80,
348 .id = 0x35,
353 .reg = 0x22c,
357 .reg = 0x318,
359 .mask = 0xff,
360 .def = 0x80,
364 .id = 0x36,
369 .reg = 0x22c,
373 .reg = 0x314,
374 .shift = 0,
375 .mask = 0xff,
376 .def = 0x80,
380 .id = 0x39,
385 .reg = 0x320,
387 .mask = 0xff,
388 .def = 0x80,
392 .id = 0x3b,
397 .reg = 0x22c,
401 .reg = 0x348,
402 .shift = 0,
403 .mask = 0xff,
404 .def = 0x80,
408 .id = 0x3c,
413 .reg = 0x22c,
417 .reg = 0x348,
419 .mask = 0xff,
420 .def = 0x80,
424 .id = 0x3d,
429 .reg = 0x22c,
433 .reg = 0x350,
435 .mask = 0xff,
436 .def = 0x80,
440 .id = 0x44,
445 .reg = 0x230,
449 .reg = 0x370,
450 .shift = 0,
451 .mask = 0xff,
452 .def = 0x18,
456 .id = 0x46,
461 .reg = 0x230,
465 .reg = 0x374,
466 .shift = 0,
467 .mask = 0xff,
468 .def = 0x80,
472 .id = 0x47,
477 .reg = 0x230,
481 .reg = 0x374,
483 .mask = 0xff,
484 .def = 0x80,
488 .id = 0x4a,
493 .reg = 0x230,
497 .reg = 0x37c,
498 .shift = 0,
499 .mask = 0xff,
500 .def = 0x7a,
504 .id = 0x4b,
509 .reg = 0x230,
513 .reg = 0x37c,
515 .mask = 0xff,
516 .def = 0x80,
520 .id = 0x4c,
525 .reg = 0x230,
529 .reg = 0x380,
530 .shift = 0,
531 .mask = 0xff,
532 .def = 0x39,
536 .id = 0x4d,
541 .reg = 0x230,
545 .reg = 0x380,
547 .mask = 0xff,
548 .def = 0x80,
552 .id = 0x4e,
557 .reg = 0x230,
561 .reg = 0x384,
562 .shift = 0,
563 .mask = 0xff,
564 .def = 0x18,
568 .id = 0x50,
573 .reg = 0x230,
577 .reg = 0x388,
578 .shift = 0,
579 .mask = 0xff,
580 .def = 0x80,
584 .id = 0x51,
589 .reg = 0x230,
593 .reg = 0x388,
595 .mask = 0xff,
596 .def = 0x80,
600 .id = 0x54,
605 .reg = 0x230,
609 .reg = 0x390,
610 .shift = 0,
611 .mask = 0xff,
612 .def = 0x9b,
616 .id = 0x55,
621 .reg = 0x230,
625 .reg = 0x390,
627 .mask = 0xff,
628 .def = 0x80,
632 .id = 0x56,
637 .reg = 0x230,
641 .reg = 0x3a4,
642 .shift = 0,
643 .mask = 0xff,
644 .def = 0x04,
648 .id = 0x57,
653 .reg = 0x230,
657 .reg = 0x3a4,
659 .mask = 0xff,
660 .def = 0x80,
664 .id = 0x58,
670 .reg = 0x230,
674 .reg = 0x3c8,
675 .shift = 0,
676 .mask = 0xff,
677 .def = 0x1a,
681 .id = 0x59,
687 .reg = 0x230,
691 .reg = 0x3c8,
693 .mask = 0xff,
694 .def = 0x80,
698 .id = 0x5a,
703 .reg = 0x230,
707 .reg = 0x2f0,
709 .mask = 0xff,
710 .def = 0x1e,
714 .id = 0x60,
719 .reg = 0x234,
720 .bit = 0,
723 .reg = 0x3b8,
724 .shift = 0,
725 .mask = 0xff,
726 .def = 0x49,
730 .id = 0x61,
735 .reg = 0x234,
739 .reg = 0x3bc,
740 .shift = 0,
741 .mask = 0xff,
742 .def = 0x5a,
746 .id = 0x62,
751 .reg = 0x234,
755 .reg = 0x3c0,
756 .shift = 0,
757 .mask = 0xff,
758 .def = 0x49,
762 .id = 0x63,
767 .reg = 0x234,
771 .reg = 0x3c4,
772 .shift = 0,
773 .mask = 0xff,
774 .def = 0x5a,
778 .id = 0x64,
783 .reg = 0x234,
787 .reg = 0x3b8,
789 .mask = 0xff,
790 .def = 0x80,
794 .id = 0x65,
799 .reg = 0x234,
803 .reg = 0x3bc,
805 .mask = 0xff,
806 .def = 0x80,
810 .id = 0x66,
815 .reg = 0x234,
819 .reg = 0x3c0,
821 .mask = 0xff,
822 .def = 0x80,
826 .id = 0x67,
831 .reg = 0x234,
835 .reg = 0x3c4,
837 .mask = 0xff,
838 .def = 0x80,
842 .id = 0x6c,
847 .reg = 0x234,
851 .reg = 0x394,
852 .shift = 0,
853 .mask = 0xff,
854 .def = 0x1a,
858 .id = 0x6d,
863 .reg = 0x234,
867 .reg = 0x394,
869 .mask = 0xff,
870 .def = 0x80,
874 .id = 0x72,
879 .reg = 0x234,
883 .reg = 0x398,
884 .shift = 0,
885 .mask = 0xff,
886 .def = 0x80,
890 .id = 0x73,
895 .reg = 0x234,
899 .reg = 0x3c8,
900 .shift = 0,
901 .mask = 0xff,
902 .def = 0x50,
906 .id = 0x78,
911 .reg = 0x234,
915 .reg = 0x3d8,
916 .shift = 0,
917 .mask = 0xff,
918 .def = 0x23,
922 .id = 0x79,
927 .reg = 0x234,
931 .reg = 0x3d8,
933 .mask = 0xff,
934 .def = 0x80,
938 .id = 0x7a,
943 .reg = 0x234,
947 .reg = 0x3dc,
948 .shift = 0,
949 .mask = 0xff,
950 .def = 0xff,
954 .id = 0x7b,
959 .reg = 0x234,
963 .reg = 0x3dc,
965 .mask = 0xff,
966 .def = 0x80,
970 .id = 0x7e,
975 .reg = 0x234,
979 .reg = 0x3e4,
980 .shift = 0,
981 .mask = 0xff,
982 .def = 0x23,
986 .id = 0x7f,
991 .reg = 0x234,
995 .reg = 0x3e4,
997 .mask = 0xff,
998 .def = 0x80,
1002 .id = 0x80,
1007 .reg = 0xb98,
1008 .bit = 0,
1011 .reg = 0x3e0,
1012 .shift = 0,
1013 .mask = 0xff,
1014 .def = 0x2e,
1018 .id = 0x81,
1023 .reg = 0xb98,
1027 .reg = 0x3e0,
1029 .mask = 0xff,
1030 .def = 0x80,
1034 .id = 0x82,
1039 .reg = 0xb98,
1043 .reg = 0x3a0,
1044 .shift = 0,
1045 .mask = 0xff,
1046 .def = 0xff,
1050 .id = 0x83,
1055 .reg = 0xb98,
1059 .reg = 0x3a0,
1061 .mask = 0xff,
1062 .def = 0x80,
1066 .id = 0x84,
1071 .reg = 0xb98,
1075 .reg = 0x3ec,
1076 .shift = 0,
1077 .mask = 0xff,
1078 .def = 0xff,
1082 .id = 0x85,
1087 .reg = 0xb98,
1091 .reg = 0x3ec,
1093 .mask = 0xff,
1094 .def = 0x80,
1098 .id = 0x86,
1103 .reg = 0xb98,
1107 .reg = 0x3f0,
1108 .shift = 0,
1109 .mask = 0xff,
1110 .def = 0x9b,
1114 .id = 0x87,
1119 .reg = 0xb98,
1123 .reg = 0x3f0,
1125 .mask = 0xff,
1126 .def = 0x80,
1130 .id = 0x88,
1136 .reg = 0xb98,
1140 .reg = 0x3e8,
1141 .shift = 0,
1142 .mask = 0xff,
1143 .def = 0x1a,
1147 .id = 0x89,
1153 .reg = 0xb98,
1157 .reg = 0x3e8,
1159 .mask = 0xff,
1160 .def = 0x80,
1167 { .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
1168 { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
1169 { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
1170 { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
1171 { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
1172 { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
1173 { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
1174 { .name = "nvenc", .swgroup = TEGRA_SWGROUP_NVENC, .reg = 0x264 },
1175 { .name = "nv", .swgroup = TEGRA_SWGROUP_NV, .reg = 0x268 },
1176 { .name = "nv2", .swgroup = TEGRA_SWGROUP_NV2, .reg = 0x26c },
1177 { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
1178 { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 },
1179 { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
1180 { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
1181 { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
1182 { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
1183 { .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 },
1184 { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
1185 { .name = "ppcs1", .swgroup = TEGRA_SWGROUP_PPCS1, .reg = 0x298 },
1186 { .name = "dc1", .swgroup = TEGRA_SWGROUP_DC1, .reg = 0xa88 },
1187 { .name = "sdmmc1a", .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 },
1188 { .name = "sdmmc2a", .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 },
1189 { .name = "sdmmc3a", .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c },
1190 { .name = "sdmmc4a", .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 },
1191 { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
1192 { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
1193 { .name = "ppcs2", .swgroup = TEGRA_SWGROUP_PPCS2, .reg = 0xab0 },
1194 { .name = "nvdec", .swgroup = TEGRA_SWGROUP_NVDEC, .reg = 0xab4 },
1195 { .name = "ape", .swgroup = TEGRA_SWGROUP_APE, .reg = 0xab8 },
1196 { .name = "se", .swgroup = TEGRA_SWGROUP_SE, .reg = 0xabc },
1197 { .name = "nvjpg", .swgroup = TEGRA_SWGROUP_NVJPG, .reg = 0xac0 },
1198 { .name = "hc1", .swgroup = TEGRA_SWGROUP_HC1, .reg = 0xac4 },
1199 { .name = "se1", .swgroup = TEGRA_SWGROUP_SE1, .reg = 0xac8 },
1200 { .name = "axiap", .swgroup = TEGRA_SWGROUP_AXIAP, .reg = 0xacc },
1201 { .name = "etr", .swgroup = TEGRA_SWGROUP_ETR, .reg = 0xad0 },
1202 { .name = "tsecb", .swgroup = TEGRA_SWGROUP_TSECB, .reg = 0xad4 },
1203 { .name = "tsec1", .swgroup = TEGRA_SWGROUP_TSEC1, .reg = 0xad8 },
1204 { .name = "tsecb1", .swgroup = TEGRA_SWGROUP_TSECB1, .reg = 0xadc },
1205 { .name = "nvdec1", .swgroup = TEGRA_SWGROUP_NVDEC1, .reg = 0xae0 },
1244 TEGRA210_MC_RESET(AFI, 0x200, 0x204, 0),
1245 TEGRA210_MC_RESET(AVPC, 0x200, 0x204, 1),
1246 TEGRA210_MC_RESET(DC, 0x200, 0x204, 2),
1247 TEGRA210_MC_RESET(DCB, 0x200, 0x204, 3),
1248 TEGRA210_MC_RESET(HC, 0x200, 0x204, 6),
1249 TEGRA210_MC_RESET(HDA, 0x200, 0x204, 7),
1250 TEGRA210_MC_RESET(ISP2, 0x200, 0x204, 8),
1251 TEGRA210_MC_RESET(MPCORE, 0x200, 0x204, 9),
1252 TEGRA210_MC_RESET(NVENC, 0x200, 0x204, 11),
1253 TEGRA210_MC_RESET(PPCS, 0x200, 0x204, 14),
1254 TEGRA210_MC_RESET(SATA, 0x200, 0x204, 15),
1255 TEGRA210_MC_RESET(VI, 0x200, 0x204, 17),
1256 TEGRA210_MC_RESET(VIC, 0x200, 0x204, 18),
1257 TEGRA210_MC_RESET(XUSB_HOST, 0x200, 0x204, 19),
1258 TEGRA210_MC_RESET(XUSB_DEV, 0x200, 0x204, 20),
1259 TEGRA210_MC_RESET(A9AVP, 0x200, 0x204, 21),
1260 TEGRA210_MC_RESET(TSEC, 0x200, 0x204, 22),
1261 TEGRA210_MC_RESET(SDMMC1, 0x200, 0x204, 29),
1262 TEGRA210_MC_RESET(SDMMC2, 0x200, 0x204, 30),
1263 TEGRA210_MC_RESET(SDMMC3, 0x200, 0x204, 31),
1264 TEGRA210_MC_RESET(SDMMC4, 0x970, 0x974, 0),
1265 TEGRA210_MC_RESET(ISP2B, 0x970, 0x974, 1),
1266 TEGRA210_MC_RESET(GPU, 0x970, 0x974, 2),
1267 TEGRA210_MC_RESET(NVDEC, 0x970, 0x974, 5),
1268 TEGRA210_MC_RESET(APE, 0x970, 0x974, 6),
1269 TEGRA210_MC_RESET(SE, 0x970, 0x974, 7),
1270 TEGRA210_MC_RESET(NVJPG, 0x970, 0x974, 8),
1271 TEGRA210_MC_RESET(AXIAP, 0x970, 0x974, 11),
1272 TEGRA210_MC_RESET(ETR, 0x970, 0x974, 12),
1273 TEGRA210_MC_RESET(TSECB, 0x970, 0x974, 13),
1281 .client_id_mask = 0xff,