18 #define MC_STAT_CONTROL				0x90
19 #define MC_STAT_EMC_CLOCK_LIMIT			0xa0
20 #define MC_STAT_EMC_CLOCKS			0xa4
21 #define MC_STAT_EMC_CONTROL_0			0xa8
22 #define MC_STAT_EMC_CONTROL_1			0xac
23 #define MC_STAT_EMC_COUNT_0			0xb8
24 #define MC_STAT_EMC_COUNT_1			0xbc
32 #define MC_STAT_CONTROL_PRI_EVENT_HP		0
36 #define MC_STAT_CONTROL_FILTER_PRI_DISABLE	0
40 #define MC_STAT_CONTROL_EVENT_QUALIFIED		0
50 #define EMC_GATHER_RST				(0 << 8)
93 		.id = 0x00,
96 		.id = 0x01,
99 		.id = 0x02,
102 		.id = 0x03,
105 		.id = 0x04,
108 		.id = 0x05,
111 		.id = 0x06,
114 		.id = 0x07,
117 		.id = 0x08,
120 		.id = 0x09,
123 		.id = 0x0a,
126 		.id = 0x0b,
129 		.id = 0x0c,
132 		.id = 0x0d,
135 		.id = 0x0e,
138 		.id = 0x0f,
141 		.id = 0x10,
144 		.id = 0x11,
147 		.id = 0x12,
150 		.id = 0x13,
153 		.id = 0x14,
156 		.id = 0x15,
159 		.id = 0x16,
162 		.id = 0x17,
165 		.id = 0x18,
168 		.id = 0x19,
171 		.id = 0x1a,
174 		.id = 0x1b,
177 		.id = 0x1c,
180 		.id = 0x1d,
183 		.id = 0x1e,
186 		.id = 0x1f,
189 		.id = 0x20,
192 		.id = 0x21,
195 		.id = 0x22,
198 		.id = 0x23,
201 		.id = 0x24,
204 		.id = 0x25,
207 		.id = 0x26,
210 		.id = 0x27,
213 		.id = 0x28,
216 		.id = 0x29,
219 		.id = 0x2a,
222 		.id = 0x2b,
225 		.id = 0x2c,
228 		.id = 0x2d,
231 		.id = 0x2e,
234 		.id = 0x2f,
237 		.id = 0x30,
240 		.id = 0x31,
243 		.id = 0x32,
246 		.id = 0x33,
262 	TEGRA20_MC_RESET(AVPC,   0x100, 0x140, 0x104,  0),
263 	TEGRA20_MC_RESET(DC,     0x100, 0x144, 0x104,  1),
264 	TEGRA20_MC_RESET(DCB,    0x100, 0x148, 0x104,  2),
265 	TEGRA20_MC_RESET(EPP,    0x100, 0x14c, 0x104,  3),
266 	TEGRA20_MC_RESET(2D,     0x100, 0x150, 0x104,  4),
267 	TEGRA20_MC_RESET(HC,     0x100, 0x154, 0x104,  5),
268 	TEGRA20_MC_RESET(ISP,    0x100, 0x158, 0x104,  6),
269 	TEGRA20_MC_RESET(MPCORE, 0x100, 0x15c, 0x104,  7),
270 	TEGRA20_MC_RESET(MPEA,   0x100, 0x160, 0x104,  8),
271 	TEGRA20_MC_RESET(MPEB,   0x100, 0x164, 0x104,  9),
272 	TEGRA20_MC_RESET(MPEC,   0x100, 0x168, 0x104, 10),
273 	TEGRA20_MC_RESET(3D,     0x100, 0x16c, 0x104, 11),
274 	TEGRA20_MC_RESET(PPCS,   0x100, 0x170, 0x104, 12),
275 	TEGRA20_MC_RESET(VDE,    0x100, 0x174, 0x104, 13),
276 	TEGRA20_MC_RESET(VI,     0x100, 0x178, 0x104, 14),
292 	return 0;  in tegra20_mc_hotreset_assert()
308 	return 0;  in tegra20_mc_hotreset_deassert()
324 	return 0;  in tegra20_mc_block_dma()
330 	return mc_readl(mc, rst->status) == 0;  in tegra20_mc_dma_idling()
336 	return (mc_readl(mc, rst->reset) & BIT(rst->bit)) == 0;  in tegra20_mc_reset_status()
352 	return 0;  in tegra20_mc_unblock_dma()
371 	return 0;  in tegra20_mc_icc_set()
389 	return 0;  in tegra20_mc_icc_aggreate()
396 	unsigned int i, idx = spec->args[0];  in tegra20_mc_of_icc_xlate_extended()
420 	for (i = 0; i < mc->soc->num_clients; i++) {  in tegra20_mc_of_icc_xlate_extended()
461 	mc_writel(mc, 0x00000000, MC_STAT_CONTROL);  in tegra20_mc_stat_gather()
464 	mc_writel(mc, 0xffffffff, MC_STAT_EMC_CLOCK_LIMIT);  in tegra20_mc_stat_gather()
490 	stat.gather0.client = client0 ? client0->id : 0;  in tegra20_mc_stat_events()
496 	stat.gather1.client = client1 ? client1->id : 0;  in tegra20_mc_stat_events()
518 	for (i = 0; i < mc->soc->num_clients; i += 2) {  in tegra20_mc_collect_stats()
529 				       &stats[i + 0].events,  in tegra20_mc_collect_stats()
534 	for (i = 0; i < mc->soc->num_clients; i++) {  in tegra20_mc_collect_stats()
631 	for (i = 0; i < mc->soc->num_clients; i++) {  in tegra20_mc_stats_show()
680 	return 0;  in tegra20_mc_stats_show()
688 	return 0;  in tegra20_mc_probe()
729 			if (value & BIT(0))  in tegra20_mc_handle_irq()
773 	.client_id_mask = 0x3f,